Timer Function Control Register (Tfcr) - Hitachi SH7032 Hardware Manual

10.2.4

Timer Function Control Register (TFCR)

The timer function control register (TFCR) is an 8-bit read/write register that selects
complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation.
TFCR is initialized to H'C0 or H'40 by a reset and in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Note: * Undefined
• Bits 7 and 6 (Reserved): Bit 7 is read as undefined. Bit 6 is always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bit 6 should always be 1.
• Bits 5 and 4 (Combination Mode 1 and 0 (CMD1 and CMD0)): CMD1 and CMD0 select
complementary PWM mode or reset-synchronized mode for channels 3 and 4. Set the
complementary PWM/reset-synchronized PWM mode while the timer counter (TCNT) being
used is off. When these bits are used to set complementary PWM/reset-synchronized PWM
mode, they take priority over the PWM4 and PWM3 bits in TMDR. While the complementary
PWM/reset-synchronized PWM mode settings and the SYNC4 and SYNC3 bit settings of the
timer synchro register (TSNC) are valid simultaneously, when complementary PWM mode is
set, channels 3 and 4 should not be set to operate simultaneously (the SYNC 4 and SYNC 3
bits in TSNC should not both be set to 1).
Bit 5: CMD1 Bit 4: CMD0
0 0
1
1 0
1
236
7 6 5
— — CMD1
1 0
*
— — R/W
Description
Channels 3 and 4 operate normally
Channels 3 and 4 operate normally
Channels 3 and 4 operate together in complementary PWM
mode
Channels 3 and 4 operate together in reset-synchronized PWM
mode
4 3
CMD0 BFB4 BFA4
0 0
R/W R/W R/W
2 1 0
BFB3 BFA3
0 0 0
R/W R/W
(Initial value)