Hitachi SH7032 Hardware Manual page 17

Section Page
20.2.3 AC 522
Characteristics
(1) Clock Timing
Table 20.18 Clock
Timing
(2) Control Signal
524
Timing
Table 20.19 Control
Signal Timing
(3) Bus Timing
528
Table 20.20 Bus
Timing (1)
(3) Bus Timing
530 to
532
Table 20.20 Bus
Timing (2)
Description
12.5 MHz added and description amended
Item Symbol
EXTAL input high level t
EXH
pulse width
EXTAL input low level t
EXL
pulse width
EXTAL input rise time t
EXr
EXTAL input fall time t
EXf
Clock cycle time t
cyc
Clock high pulse width t
CH
Clock low pulse width t
CL
Clock rise time t
Cr
Clock fall time t
Cf
Reset oscillation settling t
OSC1
time
Software standby t
OSC2
oscillation settling time
12.5 MHz added and description amended
Item Symbol
RES setup time
t
RESS
RES pulse width
t
RESW
NMI reset setup time t
NMIRS
NMI reset hold time t
NMIRH
NMI setup time t
NMIS
NMI hold time t
NMIH
IRQ0–IRQ7 setup time
t
IRQES
(edge detection)
IRQ0–IRQ7 setup time
t
IRQLS
(level detection)
IRQ0–IRQ7 hold time
t
IRQEH
IRQOUT output delay
t
IRQOD
time
Bus request setup time t
BRQS
Bus acknowledge delay t
BACD1
time 1
Bus acknowledge delay t
BACD2
time 2
Bus 3-state delay time t
BZD
Description amended
6
Read data access time 2 *
t
ACC2
Newly added
12.5 MHz 20 MHz
Min Max Min Max
22 — 15 —
22 — 15 —
— 10 — 5
— 10 — 5
80 500 50 250
30 — 20 —
30 — 20 —
— 10 — 5
— 10 — 5
10 — 10 —
10 — 10 —
12.5 MHz 20 MHz
Min Max Min Max
320 — 200 —
20 — 20 —
320 — 200 —
320 — 200 —
160 — 100 —
80 — 50 —
160 — 100 —
160 — 100 —
80 — 50 —
— 80 — 50
80 — 50 —
— 80 — 50
— 80 — 50
— 80 — 50
× (n+2) –
t — ns
cyc
3
30 *
Edition
6
Unit Figures
ns 20.45
ns
ns
ns
ns 20.45, 20.46
ns 20.46
ns
ns
ns
ms 20.47
ms
6
Unit Figure
ns 20.48
t
cyc
ns
ns
ns 20.49
ns
ns
ns
ns
ns 20.50
ns 20.51
ns
ns
ns
6
20.53, 20.54, 20.57–20.59
6