Cases In Which Exceptions Are Not Accepted; Immediately After Delayed Branch Instruction; Immediately After Interrupt-Disabling Instruction - Hitachi SH7032 Hardware Manual

4.6

Cases in which Exceptions are Not Accepted

In some cases, address errors and interrupts that directly follow a delayed branch instruction or
interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this
occurs, the exception is accepted when an instruction that can accept the exception is decoded.
Table 4.9 Cases in which Exceptions are Not Accepted
Case

Immediately after delayed branch instruction *

Immediately after interrupt-disabled instruction *
X: Not accepted
O: Accepted
Notes: *1 Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE
*2 Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
4.6.1 Immediately after Delayed Branch Instruction
Address errors and interrupts are not accepted when an instruction in a delay slot immediately
following a delayed branch instruction is decoded. The delayed branch instruction and the
instruction in the delay slot are therefore always executed one after the other. Exception handling
is never inserted between them.
4.6.2

Immediately after Interrupt-Disabling Instruction

Interrupts are not accepted when the instruction immediately following an interrupt-disabled
instruction is decoded. Address errors are accepted, however.
Address Error
1
X
2
O
Exception Source
Interrupt
X
X
63