Reset Control/Status Register (Rstcsr) - Hitachi H8S/2215 Series Hardware Manual

12.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized
to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by
overflows.
Bit Bit Name
7 WOVF
6 RSTE
5 RSTS
4 – 0 —
Note: * The write value should always be 0 to clear this flag.
Rev. 3.0, 10/02, page 350 of 686
Initial Value R/W
0 R/(W)*
0 R/W
0 R/W
1 —
Description
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and the write value should always be 0.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
Reset Select
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
Reserved
These bits are always read as 1 and cannot be
modified.