Transmit Shift Register; Transmit Data Register - Hitachi SH7032 Hardware Manual

The CPU can read but not write to RDR. RDR is initialized to H'00 by a reset and in standby
mode.
Bit:
Bit name:
Initial value:
R/W:
13.2.3

Transmit Shift Register

The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit
0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from
TDR into TSR and starts transmitting again. If the TDRE bit in SSR is 1, however, the SCI does
not load the TDR contents into TSR. The CPU cannot read or write to TSR directly.
Bit:
Bit name:
R/W:
13.2.4

Transmit Data Register

The transmit data register (TDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written
in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in TDR during serial transmission from TSR.
The CPU can always read and write to TDR. TDR is initialized to H'FF by a reset and in standby
mode.
Bit:
Bit name:
Initial value:
R/W:
7 6
0 0
R R
7 6
— — —
7 6
1 1
R/W R/W R/W
5 4 3
0 0 0
R R R
5 4 3
— —
5 4 3
1 1 1
R/W R/W
2 1
0 0
R R
2 1
— — —
2 1
1 1
R/W R/W R/W
0
0
R
0
0
1
353