Stack Status After Exception Handling - Hitachi SH7032 Hardware Manual

4.7

Stack Status after Exception Handling

Table 4.10 shows the stack after exception handling.
Table 4.10 Stack after Exception Handling
Type Stack Status
Address
Address of
error
instruction
SP
after instruc-
tion that has
finished
executing
Trap
Address of
instruc-
instruction
SP
tion
after TRAPA
instruction
General
illegal
Start add-
SP
ress of
instruc-
illegal
tion
instruction
Note: Stack status is based on a bus width of 16 bits.
64
Upper 16 bits
Lower 16 bits
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Type Stack Status
Interrupt
Address of
instruction
SP
after instruc-
tion that
has finished
executing
Illegal
Branch
slot
destination
SP
instruc-
address of
tion
delayed
branch
instuction
Upper 16 bits
Lower 16 bits
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SR
Upper 16 bits
Lower 16 bits