Receive Data Register (Rdr) Sci - Hitachi SH7032 Hardware Manual

Table A.11 SSR Bit Functions (cont)
Bit Bit name
2 Transmit end
(TEND)
1 Multiprocessor
bit (MPB)
0 Multiprocessor 0
bit transfer
(MPBT)
A.2.6 Receive Data Register (RDR)
• Start Address: H'5FFFEC5 (channel 0), H'5FFFECD (channel 1)
• Bus Width: 8/16
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit Bit name
7–0 (Receive serial data storage)
570
Value Description
0 Indicates that transmission is in progress
Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1;
(2) Data written to TDR by DMAC
1 Indicates that transmission has ended
Set Conditions: (1) Reset or standby mode; (2) TE bit in SCR is 0;
(3) TDRE = 1 when the final bit of a 1-byte serial transmit character
is transmitted
0 Indicates that data with multiprocessor bit = 0 has been received
1 Indicates that data with multiprocessor bit = 1 has been received
0 transmitted as the multiprocessor bit
1 1 transmitted as the multiprocessor bit
7 6
0 0
R R
Description
Store the serial data received
5 4 3
0 0 0
R R R
(Initial value)
(Initial value)
(Initial value)
SCI
2 1 0
0 0 0
R R R