Timer Control/Status Register (Tcsr)-H'ff91 - Hitachi H8/329 Series Hardware Manual

Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled.
1 Timer overflow interrupt request (FOVI) is enabled.
Bit 0—Reserved: This bit cannot be modified and is always read as "1."
6.2.5 Timer Control/Status Register (TCSR)—H'FF91
Bit 7
ICFA
Initial value 0
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
The TCSR is an 8-bit readable and partially writable* register that contains the seven interrupt flags
and specifies whether to clear the counter on compare-match A (when the FRC and OCRA values
match).
Note: * Software can write a "0" in bits 7 to 1 to clear the flags, but cannot write a "1" in these
bits.
The TCSR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to "1" to flag an input capture A
event. If BUFEA = "0," ICFA indicates that the FRC value has been copied to ICRA. If BUFEA =
"1," ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value
has been copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7
ICFA Description
0 To clear ICFA, the CPU must read ICFA after it
has been set to "1," then write a "0" in this bit.
1 This bit is set to 1 when an FTIA input signal causes the FRC
value to be copied to ICRA.
6 5 4
ICFB ICFC ICFD
0 0 0
122
3 2
OCFA OCFB OVF
0 0
(Initial value)
1 0
CCLRA
0 0
R/W
(Initial value)