Hitachi SH7032 Hardware Manual page 310

TCNT3
GRA3
IMFA
Buffer transfer
signal (BR to GR)
GR
TCNT4
OVF
Buffer transfer
signal (BR to GR)
GR
The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1
for underflows only. The buffer register (BR) set for the buffer operation is transferred to GR upon
compare match A3 (when incrementing) or TCNT4 underflow.
N–1 N
Set to 1
Buffer transfer performed
Figure 10.36 Overshoot Timing
H' 0001 H' 0000
Set to 1
Buffer transfer performed
Figure 10.37 Undershoot Timing
N + 1 N
N
Underflow Overflow
H' FFFF H' 0000
Flag not set
N–1
Flag not set
Buffer transfer
not performed
Buffer transfer
not performed
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