Hitachi SH7032 Hardware Manual page 240

Superh risc engine
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• DREQ pin sampling timing in cycle-steal mode
In cycle-steal mode, the sampling timing is the same regardless of whether DREQ is detected
by edge or level. With edge detection, however, once the signal is sampled it will not be
sampled again until the next edge detection. Once DREQ input is detected, the next sampling
is not performed until the first state, among those DMAC bus cycles thereby produced, in
which a DACK signal is output (including the detection state itself). The next sampling occurs
immediately prior to the rising edge of the clock pulse (CK) of the third state after the bus
cycle previous to the bus cycle in which the DACK signal is output.
Figures 9.13 to 9.22 show the sampling timing of the DREQ pin in cycle-steal mode for each
bus cycle. When no DREQ input is detected at the sampling after the aforementioned DREQ
detection, the next sampling occurs in the next state in which a DACK signal is output. If no
DREQ input is detected at this time, sampling occurs at every subsequent state.
CK
DREQ
Bus cycle
CPU
CPU
CPU
DMAC
CPU
CPU
CPU
CPU
DACK
Figure 9.13 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 1 State)
205

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