Hitachi SH7032 Hardware Manual page 209

(c) Refresh cycle + bus cycle
The bus is never released during a refresh cycle and the following bus cycle ((a) or (b)
above)) (figure 8.46).
2. Bus release procedure
The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is
input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7032
and SH7034, the bus is released after the bus cycle in which BREQ is input (if BREQ is input
between bus cycles, after the bus cycle starting next).
CK
t
BREQ
BACK
RD, WR
RAS, CAS
CSn
A21 to A0
174
Refresh cycle
Cycle during which bus
is not released
Figure 8.46 Refresh Cycle and Following Bus Cycle
BRQS
Bus cycle
Strobe pin:
high-level output
The bus is released after the bus
cycle in which BREQ is input
(if BREQ is input between bus cycles,
after the bus cycle starting next).
Figure 8.47 Bus Release Procedure
1 bus cycle
t
BRQS
t
BACD1
t
BZD
t
BZD
Bus release
Address & data
strobe pins:
high impedance
t
BACD2
Bus cycle
Bus cycle restart