Usage Notes - Hitachi SH7032 Hardware Manual

9.5

Usage Notes

1. All registers other than the DMA operation register (DMAOR) and DMA channel control
registers 0–3 (CHCR0–CHCR3) should be accessed in word or longword units.
2. Before rewriting the RS0–RS3 bits in CHCR0–CHCR3, first clear the DE bit to 0 (when
rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance).
3. Even when an NMI interrupt is input when the DMAC is not operating, the NMIF bit in
DMAOR will be set.
4. Interrupt during DMAC transfer
When an interrupt occurs during DMAC transfer, the following operation takes place.
a. When an NMI interrupt is input, the DMAC stops operation and returns the bus to the
CPU. The CPU then executes the interrupt handling.
b. When an interrupt other than an NMI occurs
• When the DMAC is in burst mode
The DMAC does not return the bus to the CPU in burst mode. Therefore, even when an
interrupt is requested in DMAC operation, the CPU cannot acquire the bus with, the
result that interrupt handling is not executed. When the DMAC completes the transfer
and the CPU acquires the bus, the CPU executes interrupt handling if the interrupt
requested during DMAC transfer is not cleared.*
Note: * Clear conditions for an interrupt request:
 When an interrupt is requested from an on-chip supporting module, and the interrupt
source flag is cleared
 When an interrupt is requested by IRQ (edge detection), and the CPU begins
interrupt handling for the IRQ request source
 When an interrupt is requested by IRQ (level detection), and the IRQ interrupt
request signal returns to the high level
• When the DMAC is in cycle-steal mode
The DMAC returns the bus to the CPU every time the DMAC completes a transfer unit
in cycle-steal mode. Therefore, the CPU executes the requested interrupt handling when
it acquires the bus.
5. The CPU and DMAC leave the bus released and the operation of the chip is stopped when the
following conditions are satisfied
• The warp bit (WARP) in the bus control register (BCR) of the bus controller (BSC) is set
• The DMAC is in cycle-steal transfer mode
• The CPU accesses (reads/writes) the on-chip I/O space
Remedy: Clear the warp bit in BCR to 0 to set normal mode.
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