Hitachi SH7032 Hardware Manual page 206

CK
RES
A0–A21
RAS
CAS
RD
RES latch
timing
CK
RES
A0–A21
RAS
CAS
RD
For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM
data must be held after a reset, take one of the measures described below.
1. When resetting manually, use the watchdog timer (WDT) reset function.
2. Even if the low width of RAS becomes as short as 1.5 tcyc as shown above, use with a
frequency that satisfies the DRAM standard (t
3. Even if the low width of RAS is 1.5 tcyc, use an external circuit so that a RAS signal with a
low width of 2.5 tcyc is input in the DRAM (if the low width of RAS is higher than 2.5 tcyc,
operate so that the current waveform is input in the DRAM).
These measures are not required when DRAM data is initialized or loaded again after a manual
reset.
Tp
RES latch
timing
Manual reset
Figure 8.40 Long-Pitch Mode Read (1)
Tp
Manual reset
Figure 8.41 Long-Pitch Mode Read (2)
Tr Tc1
Row address Column address
Tr Tc1
Row address FFFF
).
RAS
Tc2
FFFF
Tc2
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