Bus State Controller (Bsc); Overview; Features - Hitachi SH7032 Hardware Manual

Section 8 Bus State Controller (BSC)
8.1

Overview

The bus state controller (BSC) divides address space and outputs control signals for all kinds of
memory and peripheral chips. BSC functions enable the chip to be connected directly to DRAM,
SRAM, ROM, and peripheral chips without the use of external circuits, simplifying system design
and allowing high-speed data transfer in a compact system.
8.1.1

Features

The BSC has the following features:
• Address space is divided into eight areas
 A maximum 4-Mbyte linear address space for each of eight areas, 0–7 (area 1 can be up to
16-Mbyte linear space when set for DRAM). (The space that can actually be used varies
with the type of memory connected.)
 Bus width (8 bits or 16 bits) can be selected by access address
 On-chip ROM and RAM is accessed in one cycle (32 bits wide)
 Wait states can be inserted using the WAIT pin
 Wait state insertion can be controlled by software. Register settings can be used to specify
the insertion of 1–4 cycles for areas 0, 2, and 6 (long wait function)
 The type of memory connected can be specified for each area
 Outputs control signals for accessing the memory and peripheral chips connected to the
area
• Direct interface to DRAM
 Multiplexes row/column addresses according to DRAM capacity
 Two types of byte access signals (dual-CAS system and dual-WE system)
 Supports burst operation (high-speed page mode)
 Supports CAS-before-RAS refresh and self-refresh
• Access control for all memory and peripheral chips
 Address/data multiplex function
• Parallel execution of external writes etc. with internal access (warp mode)
• Supports parity check and generation for data bus
 Odd parity/even parity selectable
 Interrupt request generated for parity error (PEI interrupt request signal)
• Refresh counter can be used as an interval timer
 Interrupt request generated at compare match (CMI interrupt request signal)
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