Wait State Control Register 2 (Wcr2) - Hitachi SH7032 Hardware Manual

8.2.3

Wait State Control Register 2 (WCR2)

Wait state control register 2 is a 16-bit read/write register that controls the number of states for
accessing each area with a DMA single address mode transfer and whether wait states are used.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
• Bits 15–8 (Wait State Control During Single-Mode DMA Transfer (DRW7–DRW0)): DRW7–
DRW0 determine the number of states in single-mode DMA memory read cycles for each area
and whether or not to sample the WAIT signal. Bits DRW7–DRW0 correspond to areas 7–0,
respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode
DMA memory read cycle for the corresponding area. If it is set to 1, sampling takes place.
For the external memory spaces of areas 1, 3–5, and 7, single-mode DMA memory read cycles
are completed in one state when the corresponding bits are cleared to 0. When they are set to 1,
the number of wait states is 2 plus the wait states from the WAIT signal. For the external
memory space of areas 0, 2, and 6, single-mode DMA memory read cycles are completed in
one state plus the long wait state number (set in wait state controller 3 (WCR3)) when the
corresponding bits are cleared to 0. When they are set to 1, the number of wait states is 1 plus
the long wait state; when the WAIT signal is low as well, a wait state is inserted.
The DRAM space (area 1) finishes the column address output cycle in one state (short pitch)
when the DRW1 bit is 0, and in 2 states plus the wait states from the WAIT signal (long pitch)
when DRW1 is 1. The single-mode DMA memory read cycle of the address/data multiplexed
I/O space (area 6) is 4 states plus the wait states from the WAIT signal, regardless of the
setting of the DRW6 bit.
15 14
DRW7 DRW6 DRW5
1 1
R/W R/W R/W
7 6
DWW7 DWW6 DWW5
1 1
R/W R/W R/W
13 12 11
DRW4 DRW3
1 1 1
R/W R/W
5 4 3
DWW4 DWW3
1 1 1
R/W R/W
10 9
DRW2 DRW1 DRW0
1 1
R/W R/W
2 1
DWW2 DWW1 DWW0
1 1
R/W R/W
8
1
R/W
0
1
R/W
111