Interrupt Sources And Dmac Activation - Hitachi SH7032 Hardware Manual

10.5.3

Interrupt Sources and DMAC Activation

The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts
and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are
allocated their own independently vectored addresses. When the interrupt's interrupt request flag is
set to 1 and the interrupt enable bit is set to 1, the interrupt is requested.
The channel priority order can be changed with the interrupt controller. For more information, see
section 5, Interrupt Controller (INTC). The compare match/input capture A interrupts of channels
0–3 can start the DMAC to transfer data. Table 10.17 lists the interrupt sources.
Table 10.17 ITU Interrupt Sources
Interrupt
Channel Source
0 IMIA0
IMIB0
OVI0
1 IMIA1
IMIB1
OVI1
2 IMIA2
IMIB2
OVI2
3 IMIA3
IMIB3
OVI3
4 IMIA4
IMIB4
OVI4
Note: * Indicates the initial status following a reset. The ranking of channels can be altered using
the interrupt controller.
Description
Compare match or input capture A0
Compare match or input capture B0
Overflow 0
Compare match or input capture A1
Compare match or input capture B1
Overflow 1
Compare match or input capture A2
Compare match or input capture B2
Overflow 2
Compare match or input capture A3
Compare match or input capture B3
Overflow 3
Compare match or input capture A4
Compare match or input capture B4
Overflow 4
DMAC Priority
Order *
Activation
Yes High
↑
No
No
Yes
No
No
Yes
No
No
Yes
No
No
No
↓
No
No Low
289