Register Status In Reset And Power-Down States - Hitachi SH7032 Hardware Manual

A.3

Register Status in Reset and Power-Down States

Table A.77 Register Status in Reset and Power-Down States
Category
CPU
Interrupt controller (INTC)
User break controller (UBC) BARH,BARL
Bus state controller (BSC)
Direct memory access
controller (DMAC)
Abbreviation Power On
R0–R15 Initialized
SR
GBR
VBR
MACH,MACL
PR
PC
IPRA–IPRE Initialized
ICR
Initialized
BAMRH,BAMRL
BBR
BCR Initialized
WCR1–WCR3
DCR
RCR
RTSCR
RTCNT
RTCOR
PCR
SAR0–SAR3 Initialized
DAR0–DAR3
TCR0–TCR3
CHCR0–CHCR3
DMAOR
Reset State
Manual
Initialized
Initialized
Initialized
Held
Initialized
Power-Down State
Standby Sleep
Held Held
Held Held
Held Held
Held Held
Initialized Held
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