A/D Data Register Ah-Dl (Addrah-Addrl) A/D; A/D Control/Status Register (Adcsr) A/D - Hitachi SH7032 Hardware Manual

A.2.7 A/D Data Register AH–DL (ADDRAH–ADDRL)
• Start Address: H'5FFFEE0, H'5FFFEE1, H'5FFFEE2, H'5FFFEE3, H'5FFFEE4, H'5FFFEE5,
H'5FFFEE6, H'5FFFEE7
• Bus Width: 8/16
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.8 ADDRAH–ADDRL Bit Functions
Bit Bit name
15–8 A/D data 9–2
7,6 A/D data 1, 0
A.2.8 A/D Control/Status Register (ADCSR)
• Start Address: H'5FFFEF8
• Bus Width: 8/16
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Only 0 can be written, to clear the flag.
15 14
AD9 AD8 AD7
0 0
R R
7 6
AD1 AD0
0 0
R R
Description
Stores upper 8 bits of A/D conversion result
Stores upper 2 bits of A/D conversion result
7 6
ADF ADIE ADST
0 0
R/(W) *
R/W R/W
13 12 11
AD6 AD5
0 0 0
R R R
5 4 3
— — —
0 0 0
R R R
5 4 3
SCAN CKS
0 0 0
R/W R/W
10 9
AD4 AD3 AD2
0 0
R R
2 1
— — —
0 0
R R
2 1
CH2 CH1 CH0
1 0
R/W R/W R/W
A/D
8
0
R
0
0
R
A/D
0
0
571