Timer Control/Status Register (Tcsr) - Hitachi SH7032 Hardware Manual

12.2.2

Timer Control/Status Register (TCSR)

The timer control/status register (TCSR) is an eight-bit read/write register. TCSR differs from
other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its
functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a
reset and in standby mode. Bits 2–0 are initialized to 000 by a reset, but retain their values in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
Note: * Only 0 can be written, to clear the flag.
• Bit 7 (Overflow Flag (OVF)): OVF indicates that TCNT has overflowed from H'FF to H'00 in
interval timer mode. It is not set in watchdog timer mode.
Bit 7: OVF
0
1
• Bit 6 (Timer Mode Select (WT/IT)): WT/IT selects whether to use the WDT as a watchdog
timer or interval timer. When TCNT overflows, the WDT either generates an interval timer
interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT
0
1
• Bit 5 (Timer Enable (TME)): TME enables or disables the timer.
Bit 5: TME
0
1
338
7 6
OVF WT/IT TME
0 0
R/(W)* R/W
Description
No overflow of TCNT in interval timer mode
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in interval timer mode
Description
Interval timer mode: interval timer interrupt to the CPU when TCNT
overflows
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when TCNT overflows in watchdog
timer mode.
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops
Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
5 4
— —
0 1
R/W — —
3 2 1
CKS2 CKS1
1 0 0
R/W R/W
0
CKS0
0
R/W
(Initial value)
(Initial value)
(Initial value)