Hitachi SH7032 Hardware Manual page 317

Superh risc engine

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Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register)

match signal

transfer signal

Figure 10.49 Compare Match Timing Example for Buffer Operation

Figure 10.50 shows an example of input capture operation in buffer mode between GRA and BRA

with GRA as an input capture register. TCNT is cleared by input capture B. The falling edge is

selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at

TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is

transferred to BRA. The timing is shown in figure 10.51.

Counter cleared by compare match B

Compare match A

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