Interrupt Priority Setting Register E (Ipre) Intc - Hitachi SH7032 Hardware Manual

A.2.33 Interrupt Priority Setting Register E (IPRE)
• Start Address: H'5FFFF8C
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.34 IPRE Bit Functions
Bit Bit name
15–12 (Set SCI1 priority level)
1
(Set PRT *
11–8
(Set WDT and REF *
7–4
levels)
Notes *1 PRT: Parity control section within the bus state controller. See section 8, Bus State
Controller (BSC), for more information.
*2 REF: DRAM refresh control section within the bus state controller. See section 8, Bus
State Controller (BSC), for more information.
15 14
0 0
R/W R/W R/W
7 6
0 0
R/W R/W R/W
and A/D priority levels) Sets the PRT *
2
priority
13 12 11
0 0 0
R/W R/W
5 4 3
—
0 0 0
R/W —
Description
Sets the SC1 priority level value
1
and A/D priority level values
Sets the WDT and REF *
10 9
0 0
R/W R/W R/W
2 1
— —
0 0
— —
2
priority level value
INTC
8
0
0
—
0
—
599