Refresh Timer Constant Register (Rtcor) Bsc; Timer Control/Status Register (Tcsr) Wdt - Hitachi SH7032 Hardware Manual

A.2.49 Refresh Timer Constant Register (RTCOR)
• Start Address: H'5FFFFB2
• Bus Width: 8/16/32 (read), 16 (write)
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.50 RTCOR Bit Functions
Bit Bit Name
7–0 (Compare match cycle)
A.2.50 Timer Control/Status Register (TCSR)
• Start Address: H'5FFFFB8
• Bus Width: 8 (read), 16 (write)
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Only 0 can be written, to clear the flag.
15 14
— —
0 0
— —
7 6
1 1
R/W R/W R/W
7 6
OVF WT/IT TME
0 0
R/(W) *
R/W R/W
13 12 11
— — —
0 0 0
— — —
5 4 3
1 1 1
R/W R/W
Description
Set with compare match cycle
5 4 3
— —
0 1 1
— —
10 9
— —
0 0
— —
2 1
1 1
R/W R/W R/W
2 1
CKS2 CKS1 CKS0
0 0
R/W R/W R/W
BSC
8
—
0
—
0
1
WDT
0
0
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