Hitachi SH7032 Hardware Manual page 572

CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL ,
WR (Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
Notes: *1 For t , use t
CAC1
t – t – t
cyc AD
It is not necessary to meet the t
*2 For t , use t
ACC1
It is not necessary to meet the t
*3 For t , use t
RAC1
It is not necessary to meet the t
is measured from A21—A0 or CAS, whichever is negated first.
*4 t
RDH
is measured from A21—A0, RAS, or CAS, whichever is negated first.
*5 t
RDH
Figure 20.56 (a) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Read)
T T
p r
t t
AD AD
Row address
t
RASD1
t
RDD
t
ACC1
*3
t
RAC1
× 0.65 – 19 (for 35% duty) or t
cyc
– t .
ASC RDS
RDS
– 30 instead of t
cyc
RDS
× 1.5 – 20 instead of t
cyc
RDS
T T
c c
Column address Column address Column address
t
t
ASC CP
t
RSD
t
ACP
*1
t
CAC1
*4
t
t
RDH
*2 RDS
t
t
DACD1
DACD2
x 0.5 – 19 (for 50% duty) instead of
cyc
specification as long as the t
– t – t .
cyc AD RDS
specification as long as the t
× 1.5 – t
cyc RASD1
specification as long as the t
T T
c c
Column address
t
RASD2
t
RDH
specification is met.
CAC1
specification is met.
ACC1
– t .
RDS
specification is met.
RAC1
*5
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