Data - Hitachi SH7032 Hardware Manual

Table 1.3 Pin Functions (cont)
Type Symbol
WAIT
Bus control
(cont)
RAS
CASH
CASL
RD
WRH
WRL
CS0–
CS7
AH
HBS,
LBS
WR
DREQ0,
DMAC
DREQ1
DACK0,
DACK1
16-bit
TIOCA0,
integrated
TIOCB0
timer pulse
TIOCA1,
unit (ITU)
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
Pin No. Pin No.
(FP-112) (TFP-120) I/O Name and Function
56 59
54 57
49 52
51 54
59 64
58 63
57 62
48–51, 51–54,
53–56 56–59
63 68
23, 58 24, 63
57 62
67, 69 72, 74
66, 68 71, 73
53, 55 56, 58
64, 65 69, 70
97, 98 103, 105
100, 101 107, 108
I Wait: Requests the insertion of wait states
(T ) into the bus cycle when the external
W
address space is accessed.
O Row address strobe: DRAM row-address
strobe timing signal.
O Column address strobe high: DRAM column-
address strobe timing signal. Output to access
the upper eight data bits.
O Column address strobe low: DRAM column-
address strobe timing. Output to access the
lower eight data bits.
O Read: Indicates reading of data from an
external device.
O Upper write: Indicates write access to the
upper eight bits of an external device.
O Lower write: Indicates write access to the
lower eight bits of an external device.
O Chip select 0–7: Chip select signals for
accessing external memory and devices.
O Address hold: Address hold timing signal for a
device using a multiplexed address/data bus.
O Upper/lower byte strobe: Upper and lower
byte strobe signals. (Also used as WRH and
A0.)
O Write: Brought low during write access. (Also
used as WRL.)
I DMA transfer request (channels 0 and 1):
Input pins for external DMA transfer requests.
O DMA transfer acknowledge (channels 0 and
1): Indicates that DMA transfer is
acknowledged.
I/O ITU input capture/output compare (channel 0):
Input capture or output compare pins.
I/O ITU input capture/output compare (channel 1):
Input capture or output compare pins.
I/O ITU input capture/output compare (channel 2):
Input capture or output compare pins.
I/O ITU input capture/output compare (channel 3):
Input capture or output compare pins.
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