Hitachi SH7032 Hardware Manual page 236

A21–A0
D15–D0
DACK
Figure 9.9 DMA Transfer Timing in Dual Address Mode (External Memory Space to
External Memory Space Transfer with DACK Output in Read Cycle)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TM bits in
CHCR0–CHCR3.
• Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (word or
byte) DMA transfer. When another transfer request occurs, the bus is obtained from the other
bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus is
passed to the other bus master. This is repeated until the transfer end conditions are satisfied.
Cycle-steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 9.10 shows an example of DMA transfer timing in cycle-steal mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ level detection
DREQ
Bus cycle CPU
Figure 9.10 Transfer Example in Cycle-Steal Mode (Dual Address Mode, DREQ Level
CK
Source address
CSn
RD
WRH
WRL
CPU CPU
Destination address
Bus returned to CPU
DMAC DMAC CPU
Read Write
Detection)
DMAC DMAC CPU
Read Write
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