Sci Interrupt Sources And The Dmac; Usage Notes - Hitachi SH7032 Hardware Manual

13.4

SCI Interrupt Sources and the DMAC

The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.12 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access
controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC executes
a data transfer to the transmit data register (TDR).
RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data.
RDRF is automatically cleared to 0 when the DMAC executes a data transfer to the receive data
register (RDR). ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot
start the DMAC.
TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. A TXI
interrupt indicates that transmit data writing is enabled. A TEI interrupt indicates that the transmit
operation is complete.
Table 13.12 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
13.5

Usage Notes

Note the following points when using the SCI.
TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag
indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers
data from TDR to TSR. Data can be written in TDR regardless of the status of the TDRE bit. If
new data is written in TDR when TDRE is 0, the old data stored in TDR will be lost because this
data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check
that TDRE is set to 1.
Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of the SSR status flags
when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR
contents cannot be transferred to RDR, so receive data is lost.
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
DMAC Activation
No
Yes
Yes
No
Priority
High
↑
↓
Low
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