Hitachi SH7032 Hardware Manual page 68

The following tables (arranged by instruction classification) show instruction codes, operations,
and execution states, using the format shown below.
Table 2.11 Instruction Code Format
Item Format
Instruction
OP.Sz
mnemonic
MSB ↔ LSB
Instruction
code
→, ←
Operation
summary (xx)
M/Q/T
&
|
^
~
<<n, >>n
Execution
cycle
T bit
—
Note: The table shows the minimum number of execution states. In practice, the number of
*
instruction execution states will be increased in cases such as the following:
1. When there is conflict between an instruction fetch and a data access
2. When the destination register of a load instruction (memory → register) is also used by
the following instruction
Explanation
OP: Operation code
SRC,DEST
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement *
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Direction of transfer
Memory operand
Flag bits in SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Value when no wait states are inserted
Instruction execution cycles: The execution cycles shown
in the table are minimums. The actual number of cycles
may be increased:
1. When contention occurs between instruction fetches and
data access, or
2. When the destination register of the load instruction
(memory → register) and the register used by the next
instruction are the same.
Value of T bit after instruction is executed
No change
0000: R0
0001: R1
...........
1111: R15
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