Hitachi SH7032 Hardware Manual page 103

IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
(Interrupt request)
UBC
(Interrupt request)
DMAC
(Interrupt request)
ITU
(Interrupt request)
SCI
(Interrupt request)
PRT
(Interrupt request)
A/D
(Interrupt request)
WDT
(Interrupt request)
REF
UBC: User break controller
DMAC: Direct memory access controller
ITU: 16-bit integrated timer pulse unit
SCI: Serial communication interface
PRT: Parity control unit of BSC
A/D: A/D converter
68
Input
control
IPR
ICR
IPRA–IPRE
Module bus
Figure 5.1 Block Diagram of Interrupt Controller
Priority
decision
Com-
logic
parator
Bus
interface
INTC
WDT: Watchdog timer
REF: DRAM refresh control unit of BSC
ICR: Interrupt control register
IPRA–IPRE: Interrupt priority registers A–E
SR: Status register
Interrupt request
SR
I3 I2 I1 I0
CPU