CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Notes: *1 For t
CAC1
t
– t
cyc
AD
*2 For t
ACC1
*3 For t
RAC1
is measured from A21–A0, RAS, or CAS, whichever is negated first.
*4 t
RDH
Figure 20.11 DRAM Bus Cycle (Short-Pitch, Normal Mode)
T
p
t
AD
× 0.65 – 19 (for 35% duty) or t
, use t
cyc
– t
– t
.
ASC
RDS
, use t
– 30 instead of t
cyc
× 1.5 – 20 instead of t
, use t
cyc
T
r
t
AD
Row
t
RASD1
t
RAH
t
ASC
t
RDD
t
CAC1
*2
t
ACC1
*3
t
RAC1
t
WSD3
t
WDD2
t
WPDD2
t
DACD4
× 0.5 – 19 (for 50% duty) instead of
cyc
– t
– t
.
cyc
AD
RDS
× 1.5 – t
cyc
RASD1
T
c
Column
t
RASD2
t
DS
t
CASD1
t
RSD
t
WCH
t
t
DACD1
DACD2
*1
t
RDH
t
RDS
t
WSD4
t
WCS
t
WDH
t
WPDH
t
DACD5
– t
.
RDS
*4
483