Reset Control/Status Register (Rstcsr) - Hitachi H8/3006 Hardware Manual

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources,
obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0 0 0
1
1 0
1
1 0 0
1
1 0
1
12.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
WRST
Initial value
Read/Write R/(W)
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on
Register Access.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Description
φ/2
φ /32
φ /64
φ /128
φ /256
φ /512
φ /2048
φ /4096
7 6 5
RSTOE —
0 0 1
*
R/W —
Reset output enable
Enables or disables external output of the reset signal
4 3 2
— — —
1 1 1
— — —
Reserved bits
(Initial value)
1 0
— —
1 1
— —
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