Hitachi SH7032 Hardware Manual page 14

Section Page
19.1.2 Register 460
Table 19.2 Standby
Control Register
(SBYCR)
20.1.2 DC 467
Characteristics
Table 20.2 DC
Characteristics

Table 20. 2 DC
Characteristics
Table 20.3 471
Permitted Output
Current Values
20.1.3 AC 472
Characteristics
(1) Clock Timing
Table 20.4 Clock
Timing
(2) Control Signal 474
Timing
Table 20.5 Control
Signal Timing
(3) Bus Timing 478,
479
Table 20.6 Bus
Timing (1)

Table 20.7 Bus
Timing (2)
494
Table 20.7 Bus
Timing (2)
Description
Note added
Name Abbreviation
Standby control register SBYCR
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
16.6 MHz deleted
Table of 16.6 MHz deleted
16.6 MHz deleted
16.6 MHz deleted
16.6 MHz deleted
Description amended
6
Read data access time 1 *
t
6
Read data access time 2 *
t
Read data access time from t
6
CAS 2 *
Read data access time from t
RAS 1 * 6
Read data access time from t
RAS 2 * 6
Data setup time for CAS
t
DS
CAS setup time for RAS
t
CSR
Row address hold time t
RAH
Table deleted
Description amended
Read data access time 1 * 4
t
ACC1
Read data access time 2 * 4
t
ACC2
R/W Initial Value Address*
R/W H'1F
4
– 30 *
t —
ACC1 cyc
× (n+2) –
t —
ACC2 cyc
3
30 *
× (n+1) –
t —
CAC2 cyc
3
25 *
× 1.5 – 20 —
t
RAC1 cyc
× (n+2.5)
t —
RAC2 cyc
3
– 20 *
5
0 * —
10 —
10 —
t – 44 —
cyc
× (n+2) – 44 *
2
t —
cyc
Access size
H'5FFFFBC 8, 16, 32
ns 20.8, 20.11, 20.12
ns 20.9, 20.10,
20.13–20.15
ns 20.13–20.15
ns 20.11, 20.12
ns 20.13–20.15
ns 20.11, 20.13
ns 20.16–20.18
ns 20.11, 20.13
ns 20.21, 20.24, 20.25
ns 20.22, 20.23,
20.26–20.28
Edition
6
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6
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6
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