Hitachi SH7032 Hardware Manual page 628

Table A.28 CHCR0–CHCR3 Bit Functions (cont)
Bit Bit name
11–8 Resource select bits
3–0 (RS3–RS0) (cont)
7 Acknowledge mode
1
bit (AM) *
6 Acknowledge level
1
bit (AL) *
DREQ select bit
5
1
(DS) *
4 Transfer bus mode bit
(TM)
3 Transfer size bit (TS)
2 Interrupt enable bit
(IE)
1 Transfer end flag bit
(TE)
0 DMA enable bit (DE)
Notes: *1 Only valid in channels 0 and 1.
*2 Transfer to external device from memory mapped external device or external memory
with DACK.
*3 Transfer from external device to memory mapped external device or external memory
with DACK.
*4 Dual address mode.
Value Description
1 0 1 1 IMIA3 (input capture A/compare match A interrupt
request of on-chip ITU3) *
1 1 0 0 Auto request (transfer request automatically generated
within DMAC) *
1 1 0 1 ADI (A/D conversion end interrupt request of on-chip
A/D converter)
1 1 1 0 Reserved (cannot be set)
1 1 1 1 Reserved (cannot be set)
0 DACK output in read cycle
1 DACK output in write cycle
0 DACK is active-high signal
1 DACK is active-low signal
DREQ detected at low
0
DREQ detected on falling edge
1
0 Cycle-steal mode
1 Burst mode
0 Byte (8 bits)
1 Word (16 bits)
0 Interrupt request disabled
1 Interrupt request enabled
0 DMA transferring or DMA transfer halted (Initial value)
Clear Conditions: TE bit read and then 0 written in TE
1 DMA transfer ends normally
0 DMA transfer disabled
1 DMA transfer enabled
4
4
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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