Reset Control/Status Register (Rstcsr) - Hitachi H8/3062 Hardware Manual

Single-chip microcomputer

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Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been

generated by watchdog timer overflow, and controls external output of the reset signal.

Initial value

Watchdog timer reset

Indicates that a reset signal has been generated

Notes: The method for writing to RSTCSR is different from that for general registers to prevent

inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.

Only 0 can be written in bit 7, to clear the flag.

Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by

reset signals generated by watchdog timer overflow.

Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that

TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3062 chip

internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to

initialize external system devices. Note that there is no RESO pin in the versions with on-chip

flash memory.

[Clearing conditions]

Reset signal at RES pin.

Read WRST when WRST =1, then write 0 in WRST.

[Setting condition]

Set when TCNT overflow generates a reset signal during watchdog timer operation

Reset output enable

Enables or disables external output of the reset signal

Reserved bits

(Initial value)