Hitachi SH7032 Hardware Manual page 217

• Bits 15 and 14 (Destination Address Mode Bits 1 and 0 (DM1 and DM0)): DM1 and DM0
select whether the DMA destination address is incremented, decremented, or left fixed (in the
single address mode, DM1 and DM0 are ignored when transfers are made from memory-
mapped external devices or external memory to external devices with DACK). DM1 and DM0
are initialized to 00 by a reset and in standby mode.
Bit 15: DM1
0
0
1
1
• Bits 13 and 12 (source address mode bits 1, 0 (SM1 and SM0)): SM1 and SM0 select whether
the DMA source address is incremented, decremented, or left fixed (in the single address
mode, SM1 and SM0 are ignored when transfers are made from external devices with DACK
to memory-mapped external devices or external memory). SM1 and SM0 are initialized to 00
by resets or in standby mode.
Bit 13: SM1 Bit 12: SM0
0 0
0 1
1 0
1 1
• Bits 11–8 (Resource Select Bits 3–0 (RS3–RS0)): RS3–RS0 specify which transfer requests
will be sent to the DMAC. Do not change the transfer request source unless the DMA enable
bit (DE) is 0. The RS3–RS0 bits are initialized to 0000 by a reset and in standby mode.
182
Bit 14: DM0
0
1
0
1
Description
Fixed source address (Initial value)
Source address is incremented (+1 or +2 depending on if the
transfer size is word or byte)
Source address is decremented (–1 or –2 depending on if
the transfer size is word or byte)
Reserved (illegal setting)
Description
Fixed destination address
Destination address is incremented (+1 or +2
depending on whether the transfer size is word or byte)
Destination address is decremented (–1 or –2
depending on whether the transfer size is word or byte)
Reserved (illegal setting)
(Initial value)