Hitachi SH7032 Hardware Manual page 532

CK
A21–A0
HBS, LBS
CSn
RD (Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
WRH, WRL,
WR (Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Notes: *1 For t
RDAC2
50% duty) instead of t
*2 For t
ACC2
is measured from A21–A0, CSn, or RD, whichever is negated first.
*3 t
RDH
T
1
t
AD
t
CSD1
t
RDD
t
DACD1
t
WSD1
t
WDD1
t
WPDD1
t
DACD3
× (n + 1.65) – 35 (for 35% duty) or t
, use t
cyc
× (n + 2) – t
cyc
× (n + 2) – 44 instead of t
, use t
cyc
Figure 20.22 Basic Bus Cycle: Two-State Access
T
2
*1
t
RDAC2
*2
t
ACC2
t
WSD2
t
DACD3
cyc
– t .
RDD RDS
× (n + 2) – t
cyc
t
CSD2
t
RSD
*3
t t
RDS RDH
t
DACD2
t
WDH
t
WPDH
× (n + 1.5) – 35 (for
(or t ) – t
AD CSD1 RDS480
.
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