Hitachi SH7032 Hardware Manual page 160

Table 8.7 How Space is Divided
Area Address
0 H'0000000–H'0FFFFFF
1 H'1000000–H'1FFFFFF
2 H'2000000–H'2FFFFFF
3 H'3000000–H'3FFFFFF
4 H'4000000–H'4FFFFFF
5 H'5000000–H'5FFFFFF
6 H'6000000–H'6FFFFFF
7 H'7000000–H'7FFFFFF
0 H'8000000–H'8FFFFFF
1 H'9000000–H'9FFFFFF
2 H'A000000–H'AFFFFFF
3 H'B000000–H'BFFFFFF
4 H'C000000–H'CFFFFFF
5 H'D000000–H'DFFFFFF
6 H'E000000–H'EFFFFFF
7 H'F000000–H'FFFFFFF
Notes: *1 When MD2–MD0 pins are 010 (SH7034)
*2 When MD2–MD0 pins are 000 or 001
*3 Select with MD0 pin
*4 Select with DRAME bit in BCR
*5 Divided into 8-bit and 16-bit space according to value of address bit A8. (Longword
accesses are inhibited, however, for on-chip supporting modules with bus widths of 8
bits. Some on-chip supporting modules with bus widths of 16 bits also have registers
that are only byte-accessible and registers for which byte access is inhibited. For
details, see the sections on the individual modules.)
*6 Divided into 8-bit space and 16-bit space by value of address bit A14
*7 Select with IOE bit in BCR
*8 For SH7032
*9 For SH7034
Assignable
Memory
1
On-chip ROM *
2
External memory *
External memory
4
DRAM *
External memory
External memory
External memory
On-chip supporting
modules
External memory * 7
Multiplexed I/O
External memory
1
On-chip ROM *
2
External memory *
External memory
4
DRAM *
External memory
External memory
External memory
External memory
External memory
On-chip RAM
Capacity Bus
(Linear Space) Width
64 kB 32
8/16 *
4 MB
4 MB 8
16 MB 8
4 MB 8
4 MB 8
4 MB 8
8/16 *
512 B
8/16 *
4 MB
4 MB
4 MB 8
64 kB 32
8/16 *
4 MB
4 MB 16
16 MB 16
4 MB 16
4 MB 16
4 MB 16
4 MB 16
4 MB 16
8 9
8 kB * , 4 kB *
32
CS Output
—
CS0
3
CS1
RAS CAS
CS2
CS3
CS4
5
—
CS6
6
CS7
—
CS0
3
CS1
RAS CAS
CS2
CS3
CS4
CS5
CS6
—
125