Hitachi SH7032 Hardware Manual page 72

Table 2.13 Arithmetic Instructions (cont)
Instruction
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.W @Rm+,@Rn+
MULS Rm,Rn
MULU Rm,Rn
NEG Rm,Rn
NEGC Rm,Rn
SUB Rm,Rn
SUBC Rm,Rn
SUBV Rm,Rn
Note: * The normal minimum number of cycles (numbers in parenthesis represent the number of
cycles when there is contention with preceding or following instructions).
Instruction Code
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0100nnnnmmmm1111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
A word in Rm is sign-
extended → Rn
A byte in Rm is zero-
extended → Rn
A word in Rm is zero-
extended → Rn
Signed operation of
(Rn) × (Rm) + MAC →
MAC
Signed operation of
Rn × Rm → MAC
Unsigned operation of
Rn × Rm → MAC
0–Rm → Rn
0–Rm–T → Rn,
Borrow → T
Rn–Rm → Rn
Rn–Rm–T → Rn,
Borrow → T
Rn–Rm → Rn,
Underflow → T
Execution
Cycles T Bit
1 —
1 —
1 —
3/(2) *
—
1–3 *
—
1–3 *
—
1 —
1 Borrow
1 —
1 Borrow
1 Underflow
37