Parity Check And Generation - Hitachi SH7032 Hardware Manual

memory space access. These types can be selected using the BAS bit in BCR. See section 8.4.3,
Byte Access Control, for details.
8.7

Parity Check and Generation

The BSC can check and generate parity for data input and output to or from the DRAM space of
area 1 and the external memory space of area 2.
To check and generate parity, select the space (DRAM space only, or DRAM space and area 2) for
which parity is to be checked and generated using the parity check enable bits (PCHK1 and
PCHK0) in the parity control register, and select odd or even parity with the parity polarity bit
(PEO).
When data is input from the space selected with the PCHK1 and PCHK0 bits, the BSC checks the
PEO bit to see if the polarity of the DPH pin input (upper byte parity data) is accurate for the
AD15–AD8 pin input (upper byte data) or if the DPL pin input (lower byte parity data) is accurate
for the AD7–AD0 pin input (lower byte data). If the check indicates that either the upper or lower
byte parity is incorrect, a parity error interrupt is produced (PEI).
When outputting data to the space selected with the PCHK1 and PCHK0 bits, the BSC outputs
parity data output of the polarity set in the PEO bit from the DPH pin for the AD15–AD8 pin
output (upper byte data) or from the DPL pin for the AD7–AD0 pin input (lower byte data) using
the same timing as the data output.
The BSC is also able to force parity output for use in testing the system's parity error check
function. When the parity force output bit (PFRC) in PCR is set to 1, a high level is forcibly output
from the DPH and DPL pins when data is output to the space selected with the PCHK1 and
PCHK0 bits.
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