Hitachi SH7032 Hardware Manual page 340

Table 10.21 ITU Operating Modes (Channel 3) (cont)
TSNC
Operating
Mode Sync MDF FDIR PWM
√ *
2
Comple- —
mentary
PWM mode
√
Reset —
synchron-
ized PWM
mode
√
Buffer —
(BRA)
√
Buffer —
(BRB)
√: Settable, —: Setting does not affect current mode
Notes: *1 In PWM mode, the input capture function cannot be used. When compare match A and
compare match B occur simultaneously, the compare match signal is inhibited.
*2 When set for complementary PWM mode, do not simultaneously set channel 3 and
channel 4 to function synchronously.
*3 Counter clearing by input capture A cannot be used when reset-synchronized PWM
mode is set.
*4 Clock selection when complementary PWM mode is set should be the same for
channels 3 and 4.
TMDR TFCR
Reset
Comp Sync
PWM PWM Buffer
— — CMD1 CMD1
= 1 = 1
CMD0 CMD0
= 0 = 0
— — CMD1 CMD1
= 1 = 1
CMD0 CMD0
= 1 = 1
√ √ √
—
√ √ √
—
Register Setting
TOCR
Output
Level
Select IOA
√ √
—
√ √
—
√
BFA3 = —
1,
others:
don't
care
√
BFB3 = —
1,
others:
don't
care
TIOR3 TCR3
Clear
IOB Select
— CCLR1
= 0
CCLR0
= 0
— CCLR1
= 0
CCLR0
= 1
√ √
√ √
Clock
Select
√ *
4
√
√
√
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