Page 1 H8/3867 Series H8/3867 HD6473867, HD6433867 H8/3866 HD6433866 H8/3865 HD6433865 H8/3864 HD6433864 H8/3863 HD6433863 H8/3862 HD6433862 H8/3827 Series H8/3827 HD6473827, HD6433827 H8/3826 HD6433826 H8/3825 HD6433825 H8/3824 HD6433824 H8/3823 HD6433823 H8/3822 HD6433822 Hardware Manual ADE-602-142B Rev. 3 2/1/99 Hitachi Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 List of Items Revised or Added for This Version Page Item Description Table 1-1 Features / CPU Change in (2) High-speed calculation specification Table 1-1 Features / Clock pulse Change in specification generators Table 1-1 Features / LCD drive power Addition supply Figure 1-1 Block Diagram...
Page 4 Page Item Description 10.2.5 Serial Mode Register (SMR) Addition of description in Notes / Bits 1 and 0 Table 10-4 Relation between n Addition of description in Notes and Clock Table 10-5 Maximum Bit Rate for Each Modification of Notes Frequency (Asynchronous Mode) Table 10-7 Relation between n Addition of description in Notes...
Page 5 Preface The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3867 Series and H8/3827 Series have a system-on-a-chip architecture that includes such peripheral functions as a as an LCD controller/driver, six timers, a 14-bit PWM, a two-channel seri- al communication interface, and an A/D converter.
Page 6: Table Of Contents
Contents Section 1 Overview ......................Overview......................... Internal Block Diagram ....................Pin Arrangement and Functions ..................1.3.1 Pin Arrangement....................1.3.2 Pin Functions ...................... Section 2 ........................13 Overview......................... 13 2.1.1 Features....................... 13 2.1.2 Address Space..................... 14 2.1.3 Register Configuration..................14 Register Descriptions...................... 15 2.2.1 General Registers....................
Page 7 Application Notes ......................53 2.9.1 Notes on Data Access ..................53 2.9.2 Notes on Bit Manipulation.................. 55 2.9.3 Notes on Use of the EEPMOV Instruction............61 Section 3 Exception Handling ..................63 Overview......................... 63 Reset ..........................63 3.2.1 Overview......................63 3.2.2 Reset Sequence ....................
Page 8 Watch Mode........................106 5.4.1 Transition to Watch Mode .................. 106 5.4.2 Clearing Watch Mode..................106 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........106 Subsleep Mode........................ 107 5.5.1 Transition to Subsleep Mode ................107 5.5.2 Clearing Subsleep Mode..................107 Subactive Mode ......................
Page 9 8.2.4 Pin States ......................140 8.2.5 MOS Input Pull-Up..................... 140 Port 3 ..........................141 8.3.1 Overview......................141 8.3.2 Register Configuration and Description ............. 141 8.3.3 Pin Functions ...................... 145 8.3.4 Pin States ......................147 8.3.5 MOS Input Pull-Up..................... 147 Port 4 ..........................148 8.4.1 Overview......................
Page 10 8.11 Input/Output Data Inversion Function................170 8.11.1 Overview......................170 8.11.2 Register Configuration and Descriptions............170 Section 9 Timers ....................... 173 Overview......................... 173 Timer A........................... 175 9.2.1 Overview......................175 9.2.2 Register Descriptions..................177 9.2.3 Timer Operation....................181 9.2.4 Timer A Operation States ................... 182 Timer C...........................
Page 11 10.1.1 Features....................... 249 10.1.2 Block diagram..................... 251 10.1.3 Pin configuration ....................252 10.1.4 Register configuration ..................252 10.2 Register Descriptions...................... 252 10.2.1 Receive shift register (RSR) ................252 10.2.2 Receive data register (RDR)................253 10.2.3 Transmit shift register (TSR)................253 10.2.4 Transmit data register (TDR)................
Page 12 12.2 Register Descriptions...................... 315 12.2.1 A/D Result Registers (ADRRH, ADRRL) ............315 12.2.2 A/D Mode Register (AMR) ................315 12.2.3 A/D Start Register (ADSR) ................317 12.2.4 Clock Stop Register 1 (CKSTPR1) ..............317 12.3 Operation ........................319 12.3.1 A/D Conversion Operation ................. 319 12.3.2 Start of A/D Conversion by External Trigger Input ...........
Page 13 15.2.2 DC Characteristics ....................363 15.2.3 AC Characteristics ....................369 15.2.4 A/D Converter Characteristics................372 15.2.5 LCD Characteristics.................... 373 15.3 Operation Timing......................374 15.4 Output Load Circuit......................378 15.5 Resonator Equivalent Circuit..................378 Appendix A CPU Instruction Set .................. 379 Instructions ........................
Page 14: Section 1 Overview
The H8/3867 and H8/3827 are also available in a ZTAT™* version with on-chip PROM which can be programmed as required by the user. Table 1-1 summarizes the features of the H8/3867 Series and H8/3827 Series. Note: * ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd. Table 1-1 Features Item...
Page 15 Table 1-1 Features (cont) Item Description Interrupts 36 interrupt sources • 13 external interrupt sources (IRQ to IRQ , WKP to WKP • 23 internal interrupt sources Clock pulse generators Two on-chip clock pulse generators • System clock pulse generator: 0.4 to 6 MHz •...
Page 16 Table 1-1 Features (cont) Item Description Timers • Timer C: 8-bit timer — Count-up/down timer with selection of seven internal clock signals or event input from external pin — Auto-reloading • Timer F: 16-bit timer — Can be used as two independent 8-bit timers —...
Page 17 Table 1-1 Features (cont) Item Specification Product lineup Product Code Mask ROM ZTAT Version Version Package ROM/RAM Size HD6433862H, — 80-pin QFP (FP-80A) ROM 16 kbytes HD6433822H RAM 1 kbyte HD6433862F, — 80-pin QFP (FP-80B) HD6433822F HD6433862W, — 80-pin TQFP (TFP-80C) HD6433822W HD6433863H, —...
Page 18: Internal Block Diagram
1.2 Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3867 Series and H8/3827 Series. /TMOW /TMOFL H8/300L /TMOFH /TMIG /IRQ /ADTRG /IRQ /TMIC /COM /IRQ /COM /IRQ /TMIF /COM (60k/48k/40k/32k (2k/1k) /COM /PWM 24k/16k) /SEG /RESO /SEG Serial /SCK Timer - A...
Page 19: Pin Arrangement And Functions
1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3867 Series and H8/3827 Series pin arrangement is shown in figures 1-2 and 1-3. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /SEG25 /WKP /SEG4...
Page 20 64 63 62 61 60 59 58 57 56 55 53 52 51 50 49 48 47 46 45 44 43 42 41 /SEG27 /WKP /SEG2 /SEG28 /WKP /SEG1 /SEG29/M /COM1 /SEG30/DO /COM2 /SEG31/CL /COM3 /SEG32/CL /COM4 /SCK /RXD /TXD /IRQ /AEVL /AEVH...
Page 21: Pin Functions
1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3864 Series. Table 1-2 Pin Functions Pin No. FP-80A Type Symbol TFP-80C FP-80B Name and Functions Power Input Power supply: All V pins should be source pins CV connected to the system power supply. See section 14, Power Supply Circuit.
Page 22 Table 1-2 Pin Functions (cont) Pin No. FP-80A Type Symbol TFP-80C FP-80B Name and Functions System TEST Output Test pin: This pin is reserved and control cannot be used. It should be connected to V Interrupt Input IRQ interrupt request 0 to 4: These pins are input pins for edge-sensitive external interrupts, with a selection of rising or...
Page 23 Table 1-2 Pin Functions (cont) Pin No. FP-80A Type Symbol TFP-80C FP-80B Name and Functions 14-bit Output 14-bit PWM output: This is an output PWM pin pin for waveforms generated by the 14-bit PWM I/O ports 3 to 1, Input Port B: This is an 8-bit input port.
Page 24 Table 1-2 Pin Functions (cont) Pin No. FP-80A Type Symbol TFP-80C FP-80B Name and Functions Serial Input SCI3-1 receive data input: communi- This is the SCI31 data input pin. cation Output SCI3-1 transmit data output: interface This is the SCI31 data output pin. (SCI) SCI3-1 clock I/O: This is the SCI31 clock I/O pin.
Page 25: Cpu
Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 26: Address Space
2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 27: Register Descriptions
2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
Page 28 Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions).
Page 29: Initial Register Values
2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 30: Data Formats In General Registers
2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. Data Format 1-bit data don’t care 1-bit data don’t care Byte data don’t care Byte data don’t care Word data...
Page 31: Memory Data Formats
2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed.
Page 32: Addressing Modes
2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 33 Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.
Page 34: Effective Address Calculation
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255).
Page 35 Table 2-2 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) Register direct, Rn Operand is contents of registers indicated by rm/rn Register indirect, @Rn Contents (16 bits) of register indicated by rm Register indirect with displacement, Contents (16 bits) of register @(d:16, Rn) indicated by rm...
Page 36 Table 2-2 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) Absolute address H'FF @aa:8 @aa:16 Immediate #xx:8 Operand is 1- or 2-byte immediate data #xx:16 Program-counter relative PC contents @(d:8, PC) Sign extension disp disp...
Page 37 Table 2-2 Effective Address Calculation (cont) Addressing Mode and Instruction Format Effective Address Calculation Method Effective Address (EA) Memory indirect, @@aa:8 H'00 Memory contents (16 bits) Notation: rm, rn: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address...
Page 38: Instruction Set
2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Instructions Number Data transfer MOV, PUSH , POP Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT...
Page 39 Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 40: Data Transfer Instructions
2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 41 Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@–Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @–SP Notation: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer Instruction Codes...
Page 42: Arithmetic Operations
2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Page 43: Logic Operations
2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 44 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Notation:...
Page 45: Bit Manipulations
2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 46 Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 47 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand:...
Page 48 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Notation: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont)
Page 49: Branching Instructions
2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 50 disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Notation: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes...
Page 51: System Control Instructions
2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Page 52: Block Data Transfer Instruction
RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Notation: Operation field Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction Size...
Page 53 Notation: Operation field Figure 2-10 Block Data Transfer Instruction Code...
Page 54: Basic Operational Timing
2.6 Basic Operational Timing CPU operation is synchronized by a system clock (ø) or a subclock (ø ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is called one state.
Page 55: Access To On-Chip Peripheral Modules
2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 56 Three-state access to on-chip peripheral modules Bus cycle state state state ø or ø Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access)
Page 57: Cpu States
2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode.
Page 58: Program Execution State
Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs occurs source handling occurs complete Program halt state Program execution state SLEEP instruction executed Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Page 59: Memory Map
2.8 Memory Map 2.8.1 Memory Map The memory map of the H8/3862 and H8/3822 is shown in figure 2-16 (1), that of the H8/3863 and H8/3823 in figure 2-16 (2), that of the H8/3864 and H8/3824 in figure 2-16 (3), that of the H8/3865 and H8/3825 in figure 2-16 (4), that of the H8/3866 and H8/3826 in figure 2-16 (5), and that of the H8/3867 and H8/3827 in figure 2-16 (6).
Page 60 H'0000 Interrupt vector area H'0029 H'002A 24 kbytes On-chip ROM (24576 bytes) H'5FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM 1024 bytes H'FB7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (2) H8/3863 and H8/3823 Memory Map...
Page 61 H'0000 Interrupt vector area H'0029 H'002A 32 kbytes On-chip ROM (32768 bytes) H'7FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM 2048 bytes H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (3) H8/3864 and H8/3824 Memory Map...
Page 62 H'0000 Interrupt vector area H'0029 H'002A 40 kbytes On-chip ROM (40960 bytes) H'9FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (4) H8/3865 and H8/3825 Memory Map...
Page 63 H'0000 Interrupt vector area H'0029 H'002A 48 kbytes On-chip ROM (49152 bytes) H'BFFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (5) H8/3866 and H8/3826 Memory Map...
Page 64 H'0000 Interrupt vector area H'0029 H'002A 60 kbytes On-chip ROM (60928 bytes) H'EDFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 2048 bytes On-chip RAM H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2-16 (6) H8/3867 and H8/3827 Memory Map...
Page 65: Application Notes
2.9 Application Notes 2.9.1 Notes on Data Access Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 66 Access States Word Byte H'0000 Interrupt vector area (42 bytes) H'0029 H'002A 32kbytes On-chip ROM H'7FFF Not used — — — H'F740 LCD RAM (32 bytes) H'F75F — — — Not used H'F780 On-chip RAM 2048 bytes H'FF7F* Not used —...
Page 67: Notes On Bit Manipulation
2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write-only bits, and when the instruction accesses an I/O port.
Page 68 Example 2: BSET instruction executed designating port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P3 to high-level output.
Page 69 As a result of this operation, bit 0 in PDR3 becomes 1, and P3 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3.
Page 70 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 71 [A: Prior to executing BCLR] MOV. B #3F, The PCR3 value (H'3F) is written to a work area in memory MOV. B R0L, @RAM0 (RAM0) as well as to PCR3. MOV. B R0L, @PCR3 Input/output Input Input Output Output Output Output Output Output...
Page 72 Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter and timer load register C TCC/TLC H'FFB5 Port data register 1* PDR1 H'FFD4 Port data register 3*...
Page 73: Notes On Use Of The Eepmov Instruction
2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ←...
Page 74: Exception Handling
Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3864 Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling High...
Page 75 When system power is turned on or off, the RES pin should be held low. Figure 3-1 shows the reset sequence starting from RES input. Reset cleared Program initial instruction prefetch Vector fetch Internal processing ø Internal address bus Internal read signal Internal write signal...
Page 76: Interrupt Immediately After Reset
3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset.
Page 77 Table 3-2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 Timer A Timer A overflow H'0016 to H'0017 Asynchronous...
Page 78: Interrupt Control Registers
3.3.2 Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Name Abbreviation Initial Value Address IRQ edge select register IEGR H'E0 H'FFF2 Interrupt enable register 1 IENR1 H'00 H'FFF3 Interrupt enable register 2 IENR2 H'00 H'FFF4...
Page 79 Bit 3: IRQ edge select (IEG3) Bit 3 selects the input sensing of the IRQ pin and TMIF pin. Bit 3 IEG3 Description Falling edge of IRQ and TMIF pin input is detected (initial value) Rising edge of IRQ and TMIF pin input is detected Bit 2: IRQ edge select (IEG2) Bit 2 selects the input sensing of pin IRQ...
Page 80 Interrupt enable register 1 (IENR1) IENTA — IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA Description...
Page 81 3. Interrupt enable register 2 (IENR2) IENDT IENAD — IENTG IENTFH IENTFL IENTC IENEC Initial value Read/Write IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Direct transfer interrupt enable (IENDT) Bit 7 enables or disables direct transfer interrupt requests. Bit 7 IENDT Description...
Page 82 Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3 IENTFH Description Disables timer FH interrupt requests (initial value) Enables timer FH interrupt requests Bit 2: Timer FL interrupt enable (IENTFL) Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Page 83 4. Interrupt request register 1 (IRR1) IRRTA — — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value Read/Write — Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A or to IRQ interrupt is requested.
Page 84 Interrupt request register 2 (IRR2) IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTC IRREC Initial value Read/Write Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested.
Page 85 Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG Description Clearing conditions: (initial value) When IRRTG = 1, it is cleared by writing 0 Setting conditions: When the TMIG pin is designated for TMIG input and the designated signal edge is input, or when TCG overflows while OVIE is set to 1 in TMG Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3...
Page 86 Bit 0: Asynchronous event counter interrupt request flag (IRREC) Bit 0 IRREC Description Clearing conditions: (initial value) When IRREC = 1, it is cleared by writing 0 Setting conditions: When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit counter mode Wakeup Interrupt Request Register (IWPR) IWPF7...
Page 87: External Interrupts
7. Wakeup Edge Select Register (WEGR) WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by a reset. Bit n: WKPn edge select (WKEGSn) Bit n selects WKPn pin input sensing.
Page 88: Internal Interrupts
Interrupts IRQ to IRQ are requested by input signals to pins IRQ to IRQ Interrupts IRQ to IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4 to IEG0 in IEGR. When these pins are designated as pins IRQ to IRQ in port mode register 3 and 1 and the...
Page 89: Interrupt Operations
3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Interrupt request External interrupts or internal interrupt enable...
Page 90 • If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
Page 91 Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1 IEN2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine Notation: Program counter...
Page 92 SP – 4 SP (R7) SP – 3 SP + 1 SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 93 Figure 3-5 Interrupt Sequence...
Page 94: Interrupt Response Time
3.3.6 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack...
Page 95: Application Notes
3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3864 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 96: Notes On Rewriting Port Mode Registers
3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ to IRQ , WKP...
Page 97 Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.
Page 98: Clock Pulse Generators
Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 99: System Clock Generator
4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of connecting a crystal oscillator. Ω...
Page 100 Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. Ω ±20% R = 1 M Ceramic Recommendation Frequency oscillator value Products Name 150 pF ±10% 1.0 MHz Murata CSB 1000J 30 pF ±10% 4.0 MHz Murata CSA 4.00MG Figure 4-4 Typical Connection to Ceramic Oscillator...
Page 101 4. External clock input method Connect an external clock signal to pin OSC , and leave pin OSC open. Figure 4-6 shows a typical connection. External clock input Open Figure 4-6 External Clock Input (Example) Frequency Oscillator Clock (ø Duty cycle 45% to 55% Note: The circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer.
Page 102: Subclock Generator
4.3 Subclock Generator Connecting a 32.768-kHz/38.4 kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz/38.4 kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 3. notes on board design for the system clock in 4.2.
Page 103 2. Pin connection when not using subclock When the subclock is not used, connect pin X to GND and leave pin X open, as shown in figure 4-9. Open Figure 4-9 Pin Connection when not Using Subclock 3. External clock input Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4-10.
Page 104: Prescalers
4.4 Prescalers The H8/3864 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5- bit counter using a 32.768-kHz or 38.4 kHz signal divided by 4 (ø...
Page 105: Note On Oscillators
4.5 Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT™ versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 106: Power-Down Modes
Section 5 Power-Down Modes 5.1 Overview The H8/3864 Series has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the eight operating modes. Table 5-1 Operating Modes Operating Mode Description Active (high-speed) mode...
Page 107 Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal states in each mode. Program Program Reset state execution state halt state SLEEP instruction Active Sleep (high-speed) (high-speed) Program mode mode halt state Standby mode SLEEP instruction Active Sleep...
Page 108 Table 5-2 Internal State in Each Operating Mode Active Mode Sleep Mode High- Medium- High- Medium- Watch Subactive Subsleep Standby Function Speed Speed Speed Speed Mode Mode Mode Mode System clock oscillator Functions Functions Functions Functions Halted Halted Halted Halted Subclock oscillator Functions Functions...
Page 109: System Control Registers
5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Registers Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'F0 H'FFF1 1.
Page 110 Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time.
Page 111 Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose ø /128, ø /64, ø /32, or ø /16 as the operating clock in active (medium- speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high- speed) mode or subactive mode.
Page 112 Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Page 113: Sleep Mode
5.2 Sleep Mode 5.2.1 Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON bits in SYSCR2 are cleared to 0.
Page 114: Standby Mode
5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Page 115: Oscillator Settling Time After Standby Mode Is Cleared
5.3.3 Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. • When a crystal oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time at least as long as the oscillation settling time.
Page 116: Standby Mode Transition And Pin States
5.3.4 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode.
Page 117: Watch Mode
5.4 Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted.
Page 118: Subsleep Mode
5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1.
Page 119: Subactive Mode
5.6 Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ , or WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous counter, SCI3-1, SCI3-2, IRQ to IRQ...
Page 120: Active (Medium-Speed) Mode
5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ or WKP...
Page 121: Direct Transfer
5.8 Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 122: Direct Transition Times
• Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
Page 123 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
Page 124 Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when øw/8 is selected as the CPU operating clock, and wait time = 8192 states) Notation: tosc: OSC clock cycle time Watch clock cycle time tcyc: System clock (ø) cycle time...
Page 125: Module Standby Mode
5.9 Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode.
Page 126 Table 5-5 (cont) Register Name Bit Name Operation CKSTPR2 LDCKSTP LCD module standby mode is cleared LCD is set to module standby mode PWCKSTP PWM module standby mode is cleared PWM is set to module standby mode WDCKSTP Watchdog timer module standby mode is cleared Watchdog timer is set to module standby mode AECKSTP Asynchronous event counter module standby mode is cleared...
Page 127: Rom
Section 6 ROM 6.1 Overview The H8/3862 and H8/3822 have 16 kbytes of on-chip mask ROM, the H8/3863 and H8/3823 have 24 kbytes, the H8/3864 and H8/3824 have 32 kbytes, the H8/3865 and H8/3825 have 40 kbytes, the H8/3866 and H8/3826 have 48 kbytes, and the H8/3867 and H8/3827 have 60 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data.
Page 128: H8/3867 And H8/3827 Prom Mode
6.2 H8/3867 and H8/3827 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported.
Page 129 H8/3867 and H8/3827 EPROM socket FP-80A, TFP-80C FP-80B HN27C101 (32-pin) 32, 26 34, 28 , CV TEST 5, 27 7, 29 Note: Pins not indicated in the figure should be left open. Figure 6-2 Socket Adapter Pin Correspondence (with HN27C101)
Page 130 Address in Address in MCU mode PROM mode H'0000 H'0000 On-chip PROM H'EDFF H'EDFF Uninstalled area* H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. There- fore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF.
Page 131: H8/3867 And H8/3827 Programming
6.3 H8/3867 and H8/3827 Programming The write, verify, and other modes are selected as shown in table 6-3 in H8/3867 and H8/3827 PROM mode. Table 6-3 Mode Selection in PROM Mode (H8/3867, H8/3827) Pins Mode to EO to EA Write Data input Address input Verify...
Page 132 Start Set write/verify mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V Address = 0 n = 0 → n + 1 < = 0.2 ms ± 5% n 25 Write time t No Go →...
Page 133 Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Table 6-4 DC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Test Item Symbol Unit Condition Input high- to EO...
Page 134 Table 6-5 AC Characteristics (Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C) Test Item Symbol Unit Condition Address setup time — — µs Figure 6-5 OE setup time — — µs Data setup time —...
Page 135 Figure 6-5 shows a PROM write/verify timing diagram. Write Verify Address Data Input data Output data Note: * t is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6-5 PROM Write/Verify Timing...
Page 136: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct V of 12.5 V.
Page 137: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 138: Ram
Section 7 RAM 7.1 Overview The H8/3862, H8/3863, H8/3822, and H8/3823 have 1 kbyte of high-speed static RAM on-chip, and the H8/3864, H8/3865, H8/3866, H8/3867, H8/3824, H8/3825, H8/3826, and H8/3827 have 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 139: I/O Ports
Section 8 I/O Ports 8.1 Overview The H8/3864 Series is provided with six 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8- bit input-only port, and one 1-bit input-only port. Table 8-1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data.
Page 140 Table 8-1 Port Functions Function Switching Port Description Pins Other Functions Registers Port 5 • 8-bit I/O port to P5 Wakeup input (WKP PMR5 to WKP • MOS input pull-up ), segment output LPCR option to SEG (SEG to SEG Port 6 •...
Page 141: Overview
8.2 Port 1 8.2.1 Overview Port 1 is a 8-bit I/O port. Figure 8-1 shows its pin configuration. P1 /IRQ /TMIF P1 /IRQ P1 /IRQ /TMIC P1 /IRQ /ADTRG Port 1 P1 /TMIG P1 /TMOFH P1 /TMOFL P1 /TMOW Figure 8-1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration.
Page 142 1. Port data register 1 (PDR1) Initial value Read/Write PDR1 is an 8-bit register that stores data for port 1 pins P1 to P1 . If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Page 143 Port pull-up control register 1 (PUCR1) PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 Initial value Read/Write PUCR1 controls whether the MOS pull-up of each of the port 1 pins P1 to P1 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 144 Bit 6: P1 /IRQ pin function switch (IRQ2) This bit selects whether pin P1 /IRQ is used as P1 or as IRQ Bit 6 IRQ2 Description Functions as P1 I/O pin (initial value) Functions as IRQ input pin Note: Rising or falling edge sensing can be designated for IRQ Bit 5: P1 /IRQ /TMIC pin function switch (IRQ1)
Page 145 Bit 2: P1 /TMOFH pin function switch (TMOFH) This bit selects whether pin P1 /TMOFH is used as P1 or as TMOFH. Bit 2 TMOFH Description Functions as P1 I/O pin (initial value) Functions as TMOFH output pin Bit 1: P1 /TMOFL pin function switch (TMOFL) This bit selects whether pin P1 /TMOFL is used as P1...
Page 146 8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1.
Page 147 Table 8-3 Port 1 Pin Functions (cont) Pin Functions and Selection Method /TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 in PCR1. TMIG PCR1 Pin function input pin P1 output pin TMIG input pin /TMOFH The pin function depends on bit TMOFH in PMR1 and bit PCR1 in PCR1.
Page 148 8.2.4 Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ /TMIF High- Retains Retains High- Retains Functional Functional /IRQ impedance previous previous impedance* previous /IRQ...
Page 149 8.3 Port 3 8.3.1 Overview Port 3 is a 8-bit I/O port, configured as shown in figure 8-2. P3 /AEVL P3 /AEVH P3 /TXD P3 /RXD Port 3 P3 /SCK P3 /RESO P3 /UD P3 /PWM Figure 8-2 Port 3 Pin Configuration 8.3.2 Register Configuration and Description Table 8-5 shows the port 3 register configuration.
Page 150 1. Port data register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 151 Port pull-up control register 3 (PUCR3) PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 Initial value Read/Write PUCR3 controls whether the MOS pull-up of each of the port 3 pins P3 to P3 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 152 Bit 5: Watchdog timer source clock select (WDCKS) This bit selects the watchdog timer source clock. Bit 5 WDCKS Description ø/8192 selected (initial value) øw/32 selected Bit 4: TMIG noise canceler select (NCS) This bit controls the noise canceler for the input capture input signal (TMIG). Bit 4 Description Noise cancellation function not used...
Page 153 Bit 1: P3 /UD pin function switch (SI1) This bit selects whether pin P3 /UD is used as P3 or as UD. Bit 1 Description Functions as P3 I/O pin (initial value) Functions as UD input pin Bit 0: P3 /PWM pin function switch (PWM) This bit selects whether pin P3 /PWM is used as P3...
Page 154 Table 8-9 Port 3 Pin Functions Pin Functions and Selection Method /TXD The pin function depends on bit TE in SCR3-1, bit SPC31 in SPCR, and bit PCR3 in PCR3. SPC31 PCR3 Pin function input pin output pin output pin /RXD The pin function depends on bit RE in SCR3-1 and bit PCR3 in PCR3.
Page 155 8.3.4 Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /AEVL High- Retains Retains High- Retains Functional Functional /AEVH impedance previous previous impedance* previous /TXD...
Page 156 8.4 Port 4 8.4.1 Overview Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8-3. /IRQ /TXD Port 4 /RXD /SCK Figure 8-3 Port 4 Pin Configuration 8.4.2 Register Configuration and Description Table 8-8 shows the port 4 register configuration. Table 8-8 Port 4 Registers Name Abbrev.
Page 157: Pin Functions
Port control register 4 (PCR4) — — — — — PCR4 PCR4 PCR4 Initial value Read/Write — — — — — PCR4 is an 8-bit register for controlling whether each of port 4 pins P4 to P4 functions as an input pin or output pin.
Page 158: Pin States
Table 8-9 Port 4 Pin Functions Pin Functions and Selection Method /SCK The pin function depends on bit CKE1 and CKE0 in SCR3-2, bit COM32 in SMR32, and bit PCR4 in PCR4. CKE1 CKE0 COM32 PCR4 Pin function input pin output pin output pin input pin...
Page 159 8.5 Port 5 8.5.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8-4. /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Port 5 /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Figure 8-4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description Table 8-11 shows the port 5 register configuration.
Page 160 1. Port data register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 161 Port mode register 5 (PMR5) Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5 /WKP /SEG pin function switch (WKPn) When pin P5n/WKPn/SEGn+1 is not used as SEG , these bits select whether the pin is used as P5n or WKP...
Page 162 8.5.3 Pin Functions Table 8-12 shows the port 5 pin functions. Table 8-12 Port 5 Pin Functions Pin Functions and Selection Method /WKP The pin function depends on bit WKP in PMR5, bit PCR5 in PCR5, and bits SGS3 to SGS0 in LPCR. /WKP (n = 7 to 0) SGS3 to SGS0...
Page 163: Mos Input Pull-Up
8.5.4 Pin States Table 8-13 shows the port 5 pin states in each operating mode. Table 8-13 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /WKP High- Retains Retains High- Retains Functional Functional to P5 / impedance previous previous impedance* previous /SEG...
Page 164: Overview
8.6 Port 6 8.6.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8-5. /SEG /SEG /SEG /SEG Port 6 /SEG /SEG /SEG /SEG Figure 8-5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description Table 8-14 shows the port 6 register configuration.
Page 165 Port data register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states.
Page 166: Pin Functions
8.6.3 Pin Functions Table 8-15 shows the port 6 pin functions. Table 8-15 Port 6 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in LPCR. to P6 /SEG (n = 7 to 0) SEG3 to SEGS0...
Page 167: Port 4
8.7 Port 7 8.7.1 Overview Port 7 is a 8-bit I/O port, configured as shown in figure 8-6. /SEG /SEG /SEG /SEG Port 7 /SEG /SEG /SEG /SEG Figure 8-6 Port 7 Pin Configuration 8.7.2 Register Configuration and Description Table 8-17 shows the port 7 register configuration. Table 8-17 Port 7 Registers Name Abbrev.
Page 168 1. Port data register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 169: Pin Functions
8.7.3 Pin Functions Table 8-18 shows the port 7 pin functions. Table 8-18 Port 7 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR7 in PCR7 and bits SGS3 to SGS0 in LPCR. to P7 /SEG (n = 7 to 0) SEGS3 to SEGS0...
Page 170: Port 5
8.8 Port 8 8.8.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8-7. /SEG /SEG /SEG /SEG Port 8 /SEG /SEG /SEG /SEG Figure 8-7 Port 8 Pin Configuration 8.8.2 Register Configuration and Description Table 8-20 shows the port 8 register configuration. Table 8-20 Port 8 Registers Name Abbrev.
Page 171 Port data register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 172: Pin Functions
8.8.3 Pin Functions Table 8-21 shows the port 8 pin functions. Table 8-21 Port 8 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bit PCR8 in PCR8 and bits SGX and SGS3 to SGS0 in LPCR. SEGS3 to SEGS0 000* 001*, 01**, 1***...
Page 173: Pin States
8.8.4 Pin States Table 8-22 shows the port 8 pin states in each operating mode. Table 8-22 Port 8 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /SEG High- Retains Retains High- Retains Functional Functional /SEG impedance previous previous impedance previous...
Page 174: Overview
8.9 Port A 8.9.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8-8. /COM /COM Port A /COM /COM Figure 8-8 Port A Pin Configuration 8.9.2 Register Configuration and Description Table 8-23 shows the port A register configuration. Table 8-23 Port A Registers Name...
Page 175 Upon reset, PDRA is initialized to H'F0. Port control register A (PCRA) — — — — PCRA PCRA PCRA PCRA Initial value Read/Write — — — — PCRA controls whether each of port A pins PA to PA functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 176 8.9.3 Pin Functions Table 8-24 shows the port A pin functions. Table 8-24 Port A Pin Functions Pin Functions and Selection Method /COM The pin function depends on bit PCRA in PCRA and bits SGS3 to SGS0. SEGS3 to SEGS0 0000 0000 Not 0000...
Page 177: Register Configuration And Description
8.10 Port B 8.10.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8-9. Port B Figure 8-9 Port B Pin Configuration 8.10.2 Register Configuration and Description Table 8-26 shows the port B register configuration. Table 8-26 Port B Register Name Abbrev.
Page 178: Input/Output Data Inversion Function
8.11 Input/Output Data Inversion Function 8.11.1 Overview With input pins WKP to WKP , RXD , and RXD , and output pins TXD and TXD , the data can be handled in inverted form. SCINV0 SCINV2 /RXD /RXD SCINV1 SCINV3 /TXD /TXD Figure 8.10 Input/Output Data Inversion Function...
Page 179 Bit 0: RXD pin input data inversion switch Bit 0 specifies whether or not RXD pin input data is to be inverted. Bit 0 SCINV0 Description input data is not inverted (initial value) input data is inverted Bit 1: TXD pin output data inversion switch Bit 1 specifies whether or not TXD pin output data is to be inverted.
Page 180 Bit 4: P3 /TXD pin function switch (SPC31) This bit selects whether pin P3 /TXD is used as P3 or as TXD Bit 4 SPC31 Description Functions as P3 I/O pin (initial value) Functions as TXD output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1. Bit 5: P4 /TXD pin function switch (SPC32)
Page 181: Timers
Section 9 Timers 9.1 Overview The H8/3864 Series provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9-1. Table 9-1 Timer Functions Event Waveform Name Functions...
Page 182 Table 9-1 Timer Functions (cont) Event Waveform Name Functions Internal Clock Input Pin Output Pin Remarks Asynchro- • 16-bit counter — AEVL — nous • Also usable as two AEVH event independent 8-bit counter counters • Counts events asynchronous to ø and øw...
Page 183: Timer A
9.2 Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz, from 38.4 kHz (if a 38.4 kHz crystal oscillator is connected), or from the system clock, can be output at the TMOW pin.
Page 184 2. Block diagram Figure 9-1 shows a block diagram of timer A. CWORS ø ø /4 ø ø ø /128 ø ø TMOW ø/32 ø/8192, ø/4096, ø/2048, ø/16 ø/512, ø/256, ø/128, ø/8 ø/32, ø/8 ø/4 ø IRRTA Notation: TMA: Timer mode register A TCA: Timer counter A IRRTA:...
Page 185: Register Descriptions
Register configuration Table 9-3 shows the register configuration of timer A. Table 9-3 Timer A Registers Name Abbrev. Initial Value Address Timer mode register A H'10 H'FFB0 Timer counter A H'00 H'FFB1 Clock stop register 1 CKSTPR1 H'FF H'FFFA Subclock output select register CWOSR H'FE H'FF92...
Page 186 Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz or 38.4 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
Page 187 Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 Bit 2 Bit 1 Bit 0 Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0...
Page 188 2. Timer counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode.
Page 189: Timer Operation
Subclock Output Select Register (CWOSR) Bit: CWOS — — — — — — — Initial value: Read/Write: CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by a reset. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved;...
Page 190: Timer A Operation States
2. Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA.
Page 191: Timer C
9.3 Timer C 9.3.1 Overview Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Features Features of timer C are given below. • Choice of seven internal clock sources (ø/8192, ø/2048, ø/512, ø/64, ø/16, ø/4, øw/4) or an external clock (can be used to count external events).
Page 192 2. Block diagram Figure 9-2 shows a block diagram of timer C. ø TMIC ø IRRTC Notation: : Timer mode register C : Timer counter C : Timer load register C IRRTC : Timer C overflow interrupt request flag : Prescaler S Figure 9-2 Block Diagram of Timer C...
Page 193: Register Descriptions
Pin configuration Table 9-5 shows the timer C pin configuration. Table 9-5 Pin Configuration Name Abbrev. Function Timer C event input TMIC Input Input pin for event input to TCC Timer C up/down-count selection Input Timer C up/down select Register configuration Table 9-6 shows the register configuration of timer C.
Page 194 Bit 7: Auto-reload function select (TMC7) Bit 7 selects whether timer C is used as an interval timer or auto-reload timer. Bit 7 TMC7 Description Interval timer function selected (initial value) Auto-reload function selected Bits 6 and 5: Counter up/down control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter.
Page 195 Timer counter C (TCC) TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC).
Page 196 3. Timer load register C (TLC) TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value Read/Write TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC). When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC starts counting up from that value.
Page 197: Timer Operation
9.3.3 Timer Operation Interval timer operation When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an interval up-counter without halting immediately after a reset.
Page 198 2. Auto-reload timer operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count.
Page 199: Timer C Operation States
9.3.4 Timer C Operation States Table 9-7 summarizes the timer C operation states. Table 9-7 Timer C Operation States Sub- Sub- Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby Interval Reset Functions Functions Halted Functions/ Functions/ Halted Halted Halted* Halted*...
Page 200: Timer F
9.4 Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
Page 201 2. Block diagram Figure 9-3 shows a block diagram of timer F. ø IRRTFL TCRF ø TCFL TMIF Toggle Comparator TMOFL circuit OCRFL TCFH Toggle TMOFH Match Comparator circuit OCRFH TCSRF IRRTFH Notation: TCRF: Timer control register F TCSRF: Timer control/status register F TCFH: 8-bit timer counter FH TCFL:...
Page 202 Pin configuration Table 9-8 shows the timer F pin configuration. Table 9-8 Pin Configuration Name Abbrev. Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output...
Page 203: Register Descriptions
9.4.2 Register Descriptions 16-bit timer counter (TCF) 8-bit timer counter (TCFH) 8-bit timer counter (TCFL) Bit: Initial value: Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Page 204 If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU. 2. 16-bit output compare register (OCRF) 8-bit output compare register (OCRFH) 8-bit output compare register (OCRFL) OCRF...
Page 205 Timer control register F (TCRF) Bit: TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: Read/Write: TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins.
Page 206 Bit 3: Toggle output level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description Low level (initial value) High level Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Page 207 Timer control/status register F (TCSRF) TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. TCSRF is initialized to H'00 upon reset. Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00.
Page 208 Bit 5: Timer overflow interrupt enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description TCFH overflow interrupt request is disabled (initial value) TCFH overflow interrupt request is enabled Bit 4: Counter clear H (CCLRH) In 8-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
Page 209 Bit 2: Compare match flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL Description Clearing conditions: (initial value) After reading CMFL = 1, cleared by writing 0 to CMFL Setting conditions:...
Page 210 Clock stop register 1 (CKSTPR1) Bit: — S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer F is described here. For details of the other bits, see the sections on the relevant modules.
Page 211: Cpu Interface
9.4.3 CPU Interface TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). In 16-bit mode, TCF read/write access and OCRF write access must be performed 16 bits at a time (using two consecutive byte-size MOV instructions), and the upper byte must be accessed before the lower byte.
Page 212 Figure 9-4 shows an example in which H'AA55 is written to TCF. Write to upper byte Module data bus interface (H'AA) TEMP (H'AA) TCFH TCFL Write to lower byte Module data bus interface (H'55) TEMP (H'AA) TCFH TCFL (H'AA) (H'55) Figure 9-4 Write Access to TCR (CPU →...
Page 213 Read access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU.
Page 214: Operation
9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers.
Page 215 OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU. 2. TCF increment timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (ø/32, ø/16, ø/4, or øw/4) created by dividing the system clock (ø...
Page 216 TMOFH/TMOFL output timing In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 9-6 shows the output timing. ø TMIF (when IEG3 = 1) Count input clock OCRF Compare match...
Page 217 is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock. Timer F operation modes Timer F operation modes are shown in table 9-10. Table 9-10 Timer F Operation Modes Module Operation Mode Reset...
Page 218: Application Notes
9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 16-bit timer mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
Page 219 If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped.
Page 220: Timer G
9.5 Timer G 9.5.1 Overview Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle.
Page 221 Block diagram Figure 9-7 shows a block diagram of timer G. ø Level detector øw/4 ICRGF Noise Edge TMIG canceler detector ICRGR IRRTG Notation: : Timer mode register G : Timer counter G ICRGF : Input capture register GF ICRGR : Input capture register GR IRRTG : Timer G interrupt request flag...
Page 222 Pin configuration Table 9-11 shows the timer G pin configuration. Table 9-11 Pin Configuration Name Abbrev. Function Input capture input TMIG Input Input capture input pin Register configuration Table 9-12 shows the register configuration of timer G. Table 9-12 Timer G Registers Name Abbrev.
Page 223: Register Descriptions
9.5.2 Register Descriptions Timer counter (TCG) Bit: TCG7 TCG6 TCG5 TCG4 TCG3 TCG2 TCG1 TCG0 Initial value: Read/Write: — — — — — — — — TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by bits CKS1 and CKS0 in TMG.
Page 224 Input capture register GR (ICRGR) Bit: ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value: Read/Write: ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time, IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
Page 225 Bit 7: Timer overflow flag H (OVFH) Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is high. This flag is set by hardware and cleared by software. It cannot be set by software.
Page 226 Bit 4: Input capture interrupt edge select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request. Bit 4 IIEGS Description Interrupt generated on rising edge of input capture input signal (initial value) Interrupt generated on falling edge of input capture input signal Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0) Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal.
Page 227 Clock stop register 1 (CKSTPR1) Bit: — S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value: Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer G is described here. For details of the other bits, see the sections on the relevant modules.
Page 228: Noise Canceler
9.5.3 Noise Canceler The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in PMR3. Figure 9-8 shows a block diagram of the noise canceler. Sampling clock Input capture...
Page 229 In this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9-9 Noise Canceler Timing (Example)
Page 230: Operation
9.5.4 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. Timer G functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. a.
Page 231 Following a reset, TCG starts incrementing on the ø/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the selected clock, and when it overflows from H’FF to H’00, the OVFL bit is set to 1 in TMG.
Page 232 Input capture input signal Sampling clock Noise canceler output Input capture signal R Figure 9-11 Input Capture Input Timing (with Noise Cancellation Function) 4. Timing of input capture by input capture input Figure 9-12 shows the timing of input capture by input capture input Input capture signal Input capture...
Page 233 TGC clear timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9-13 shows the timing for clearing by both edges. Input capture input signal Input capture signal F Input capture signal R H'00...
Page 234: Application Notes
by a synchronization circuit. This results in a maximum count cycle error of 1/ø (s). When øw/4 is selected as the TCG internal clock in watch mode, TCG and the noise canceler operate on the øw/4 internal clock without regard to the ø subclock (øw/8, øw/4, øw/2).
Page 235 Table 9-14 Internal Clock Switching and TCG Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from low level to low level Clock before switching Clock after switching Count clock Write to CKS1 and CKS0 Goes from low level to high level Clock before switching...
Page 236 Table 9-14 Internal Clock Switching and TCG Operation (cont) Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from high level to high level Clock before switching Clock before switching Count clock Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and TCG is incremented.
Page 237 Table 9-15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Conditions Generation of rising edge When TMIG is modified from 0 to 1 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler...
Page 238: Timer G Application Example
clearing. When switching the pin function, set the interrupt-disabled state before manipulating the port mode register, then, after the port mode register operation has been performed, wait for the time required to confirm the input capture input signal as an input capture signal (at least two system clocks when the noise canceler is not used;...
Page 239 Input capture input signal H'FF Input capture register GF Input capture register GR H'00 Counter cleared Figure 9-15 Timer G Application Example...
Page 240: Watchdog Timer
9.6 Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1.
Page 241: Register Descriptions
Register configuration Table 9-17 shows the register configuration of the watchdog timer. Table 9-17 Watchdog Timer Registers Name Abbrev. Initial Value Address Timer control/status register W TCSRW H'AA H'FFB2 Timer counter W H'00 H'FFB3 Clock stop register 2 CKSTP2 H'FF H'FFFB Port mode register 3 PMR3...
Page 242 Bit 6: Timer counter W write enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE Description Data cannot be written to TCW (initial value) Data can be written to TCW Bit 5: Bit 4 write inhibit (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW.
Page 243 Bit 2: Watchdog timer on (WDON) Bit 2 enables watchdog timer operation. Bit 2 WDON Description Watchdog timer operation is disabled (initial value) Clearing conditions: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON Watchdog timer operation is enabled Setting conditions: When TCSRWE = 1 and 0 is written in B2WI and 1 is written in WDON...
Page 244 2. Timer counter W (TCW) TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is ø/8192 or øw/32. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW.
Page 245: Timer Operation
Port mode register 3 (PMR3) PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports.
Page 246: Watchdog Timer Operation States
TCW overflow H'FF H'F8 TCW count value H'00 Start Reset H'F8 written H'F8 written in TCW in TCW Internal reset signal 512 ø clock cycles Figure 9-17 Typical Watchdog Timer Operations (Example) 9.6.4 Watchdog Timer Operation States Table 9-18 summarizes the watchdog timer operation states. Table 9-18 Watchdog Timer Operation States Sub- Sub-...
Page 247: Asynchronous Event Counter (Aec)
9.7 Asynchronous Event Counter (AEC) 9.7.1 Overview The asynchronous event counter is incremented by external event clock input. Features Features of the asynchronous event counter are given below. • Can count asynchronous events Can count external events input asynchronously without regard to the operation of base clocks ø and ø...
Page 248 2. Block diagram Figure 9-18 shows a block diagram of the asynchronous event counter. IRREC ECCSR AEVH AEVL Notation: ECCSR : Event counter control/status register : Event counter H : Event counter L AEVH : Asynchronous event input H AEVL : Asynchronous event input L : Event counter overflow interrupt request flag IRREC...
Page 249: Register Descriptions
Pin configuration Table 9-19 shows the asynchronous event counter pin configuration. Table 9-19 Pin Configuration Name Abbrev. Function Asynchronous event input H AEVH Input Event input pin for input to event counter H Asynchronous event input L AEVL Input Event input pin for input to event counter L Register configuration Table 9-20 shows the register configuration of the asynchronous event counter.
Page 250 When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000. Bit 7 Description ECH has not overflowed (initial value) Clearing conditions: After reading OVH = 1, cleared by writing 0 to OVH...
Page 251 Bit 4 Description ECH and ECL are used together as a single-channel 16-bit event counter (initial value) ECH and ECL are used as two independent 8-bit event counter channels Bit 3: Count-up enable H (CUEH) Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled and increments the counter.
Page 252 Bit 0: Counter reset control L (CRCL) Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to this bit, the counter reset is cleared and the ECL count-up function is enabled. Bit 0 CRCL Description...
Page 253 Clock stop register 2 (CKSTPR2) — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the asynchronous event counter is described here. For details of the other bits, see the sections on the relevant modules.
Page 254: Operation
9.7.3 Operation 1. 16-bit event counter operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Figure 9- 19 shows an example of the software processing when ECH and ECL are used as a 16-bit event counter.
Page 255: Asynchronous Event Counter Operation Modes
Start Set CH2 to 1 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 Figure 9-20 Example of Software Processing when Using ECH and ECL as 8-Bit Event Counters ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9-20.
Page 256: Application Notes
9.7.5 Application Notes 1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. When clear bits CUEH and CUEL to 0 in ECCSR, ECH and ECL sometimes count up.
Page 257: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface 10.1 Overview The H8/3864 Series is provided with two serial communication interfaces, SCI3-1 and SCI3-2. These two SCIs have identical functions. In this manual, the generic term SCI3 is used to refer to both SCIs. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode.
Page 258 Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length 8 bits Receive error detection Overrun errors • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously.
Page 259: Block Diagram
10.1.2 Block diagram Figure 10-1 shows a block diagram of SCI3. Internal clock (ø/64, ø/16, øw/2, ø) External Baud rate generator clock Clock Transmit/receive SCR3 control circuit SPCR Interrupt request (TEI, TXI, RXI, ERI) Notation: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register...
Page 260: Pin Configuration
10.1.3 Pin configuration Table 10-1 shows the SCI3 pin configuration. Table 10-1 Pin Configuration Name Abbrev. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 10.1.4 Register configuration Table 10-2 shows the SCI3 register configuration.
Page 261: Receive Data Register (Rdr)
RSR cannot be read or written directly by the CPU. 10.2.2 Receive data register (RDR) RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write RDR is an 8-bit register that stores received serial data. When reception of one byte of data is finished, the received data is transferred from RSR to RDR, and the receive operation is completed.
Page 262: Transmit Data Register (Tdr)
10.2.4 Transmit data register (TDR) TDR7 TDR6 TDR5 TDR4 TDR3 TDR0 TDR2 TDR1 Initial value Read/Write TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission.
Page 263 Bit 6: Character length (CHR) Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. Bit 6 Description 8-bit data/5-bit data* (initial value)
Page 264 Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Page 265: Serial Control Register 3 (Scr3)
10.2.6 Serial control register 3 (SCR3) MPIE CKE0 TEIE CKE1 Initial value Read/Write SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. SCR3 can be read or written by the CPU at any time. SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Page 266 Bit 5: Transmit enable (TE) Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5 Description Transmit operation disabled (TXD pin is I/O port) (initial value) Transmit operation enabled (TXD pin is transmit data pin) Notes: 1. Bit TDRE in SSR is fixed at 1. 2.
Page 267 Bit 2: Transmit end interrupt enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE Description Transmit end interrupt request (TEI) disabled (initial value) Transmit end interrupt request (TEI) enabled...
Page 268: Serial Status Register (Ssr)
10.2.7 Serial status register (SSR) TDRE RDRF MPBT TEND MPBR Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits.
Page 269 Bit 6: Receive data register full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF Description There is no receive data in RDR (initial value) Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF When RDR data is read by an instruction There is receive data in RDR Setting conditions:...
Page 270 Bit 4: Framing error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 Description Reception in progress or completed (initial value) Clearing conditions: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception Setting conditions: When the stop bit at the end of the receive data is checked for a value...
Page 271 Bit 2: Transmit end (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND Description Transmission in progress Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction...
Page 272 10.2.8 Bit rate register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR0 BRR2 BRR1 Initial value Read/Write BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time.
Page 273 Notes: 1. The setting should be made so that the error is not more than 1%. 2. The value set in BRR is given by the following equation: — 1 (64 × 2 × B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤...
Page 274 Table 10-5 shows the maximum bit rate for each frequency. The values shown are for active (high- speed) mode. Table 10-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting Maximum Bit Rate OSC (MHz) (bit/s) 0.0384* 31250 2.4576 38400 62500 * : When SMR is set up to CKS1 = “0”, CKS0 = “1”.
Page 275 Notes: The value set in BRR is given by the following equation: — 1 (8 × 2 × B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) OSC: Value of ø (Hz) n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10-7.) Table 10-7 Relation between n and Clock...
Page 276: Clock Stop Register 1 (Ckstpr1)
10.2.9 Clock stop register 1 (CKSTPR1) — S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Page 277: Serial Port Control Register (Spcr)
10.2.10 Serial Port Control Register (SPCR) — — SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 Initial value Read/Write — — SPCR is an 8-bit readable/writable register that performs RXD , RXD , TXD , and TXD input/output data inversion switching. SPCR is initialized to H'C0 by a reset. Bit 0: RXD pin input data inversion switch Bit 0 specifies whether or not RXD...
Page 278 Bit 3: TXD pin output data inversion switch Bit 3 specifies whether or not TXD pin output data is to be inverted. Bit 3 SCINV3 Description output data is not inverted (initial value) output data is inverted Bit 4: P3 /TXD pin function switch (SPC31) This bit selects whether pin P3...
Page 279: Operation
10.3 Operation 10.3.1 Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10-8.
Page 280 Table 10-8 SMR Settings and Corresponding Data Transfer Formats Data Transfer Format bit 7 bit 6 bit 2 bit 5 bit 3 Data Multiprocessor Parity Stop Bit COM CHR MP STOP Mode Length Length Asynchronous 8-bit data 1 bit mode 2 bits 1 bit 2 bits...
Page 281 Interrupts and continuous transmission/reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10-10. Table 10-10 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RDRF When serial reception is performed The RXI interrupt routine reads the normally and receive data is receive data transferred to RDR and...
Page 282 RSR (reception in progress) RSR↑ (reception completed, transfer) RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 10-2 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TSR (transmission in progress) TSR↓ (transmission completed, transfer) TDRE ←...
Page 283: Operation In Asynchronous Mode
10.3.2 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 284 Table 10-11 shows the 12 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10-11 Data Transfer Formats (Asynchronous Mode) Serial Data Transfer Format and Frame Length STOP 10 11 12 8-bit data...
Page 285 Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10-9 for details on clock source selection. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate.
Page 286 Figure 10-5 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 287 • Transmitting Figure 10-6 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then write transmit data to the transmit...
Page 288 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 289 • Receiving Figure 10-8 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 290 If a receive error has Start receive occurred, read bits OER, error processing Overrun error PER, and FER in SSR to processing identify the error, and after carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 291 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10-11. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received.
Page 292: Operation In Synchronous Mode
Figure 10-9 shows an example of the operation when receiving in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark state data data (idle state) Serial data 1 frame 1 frame RDRF RXI request RDRF 0 start bit ERI request in operation cleared to 0...
Page 293 Data transfer format The general data transfer format in asynchronous communication is shown in figure 10-10. Serial clock Serial Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 data Don't Don't 8 bits care care One transfer data unit (character or frame)
Page 294: Data Transfer Operations
3. Data transfer operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in 10.1.4 (3)(a). SCI3 initialization, and shown in figure 10-5. • Transmitting Figure 10-11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Page 295 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 296 • Receiving Figure 10-13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing.
Page 297 SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 298 • Simultaneous transmit/receive Figure 10-15 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write in SSR...
Page 299: Multiprocessor Communication Function
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously. 2.
Page 300 Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver specified buy the ID) MPB: Multiprocessor bit...
Page 301 Start Sets bits SPC31 and SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR).
Page 302 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 303 Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 304 Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 10-19 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10-20 shows an example of the operation when receiving using the multiprocessor format.
Page 305 Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state User RDR data read When data is not...
Page 306: Interrupts
10.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10-13. Table 10-13 SCI3 Interrupt Requests Interrupt Abbreviation...
Page 307: Application Notes
10.5 Application Notes The following points should be noted when using SCI3. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically.
Page 308 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 309 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD3x) Synchronization sampling timing Data sampling timing Figure 10-21 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). D –...
Page 310 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 311 Switching SCK function If pin SCK is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (ø) cycle immediately after it is switched.
Page 312: Section 11 14-Bit Pwm
Section 11 14-Bit PWM 11.1 Overview The H8/3864 Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features Features of the 14-bit PWM are as follows. •...
Page 313: Pin Configuration
PWDRL PWDRU ø/2 ø/4 waveform ø/8 generator ø/16 PWCR Notation: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register Figure 11-1 Block Diagram of the 14 bit PWM 11.1.3 Pin Configuration Table 11-1 shows the output pin assigned to the 14-bit PWM. Table 11-1 Pin Configuration Name Abbrev.
Page 314 11.2 Register Descriptions 11.2.1 PWM Control Register (PWCR) — — — — — — PWCR1 PWCR0 Initial value Read/Write — — — — — — PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FC. Bits 7 to 2: Reserved bits Bits 7 to 2 are reserved;...
Page 315: Pwm Data Registers U And L (Pwdru, Pwdrl)
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 Initial value Read/Write — — PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value Read/Write PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL.
Page 316 Bit 1: PWM module standby mode control (PWCKSTP) Bit 1 controls setting and clearing of module standby mode for the PWM. PWCKSTP Description PWM is set to module standby mode PWM module standby mode is cleared (initial value)
Page 317: Operation
11.3 Operation 11.3.1 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 3 (PMR3) to 1 so that pin P3 /PWM is designated for PWM output. 2. Set bits PWCR1 and PWCR0 in the PWM control register (PWCR) to select a conversion period of 131,072/ø...
Page 318 1 conversion period T = t ..t ..= t Figure 11-2 PWM Output Waveform 11.3.2 PWM Operation Modes PWM operation modes are shown in table 11-3. Table 11-3 PWM Operation Modes Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby...
Page 319: Section 12 A/D Converter
Section 12 A/D Converter 12.1 Overview The H8/3864 Series includes on-chip a resistance-ladder-based successive-approximation analog-to- digital converter, and can convert up to 8 channels of analog input. 12.1.1 Features The A/D converter has the following features. • 10-bit resolution • Eight input channels •...
Page 320: Pin Configuration
12.1.3 Pin Configuration Table 12-1 shows the A/D converter pin configuration. Table 12-1 Pin Configuration Name Abbrev. Function Analog power supply Input Power supply and reference voltage of analog part Analog ground Input Ground and reference voltage of analog part Analog input 0 Input Analog input channel 0...
Page 321: Register Descriptions
12.2 Register Descriptions 12.2.1 A/D Result Registers (ADRRH, ADRRL) ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 — — — — — — Initial value — — — — — — fixed fixed fixed fixed fixed fixed fixed fixed fixed fixed...
Page 322 Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: * The external trigger (ADTRG) edge is selected by bit INTEG4 of IEGR.
Page 323: A/D Start Register (Adsr)
12.2.3 A/D Start Register (ADSR) ADSF — — — — — — — Initial value Read/Write — — — — — — — The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1.
Page 324 Bit 4 controls setting and clearing of module standby mode for the A/D converter. ADCKSTP Description A/D converter is set to module standby mode A/D converter module standby mode is cleared (initial value)
Page 325: Operation
12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1.
Page 326: A/D Converter Operation Modes
12.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 12-3. Table 12-3 A/D Converter Operation Modes Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Reset Functions Functions Held Held Held Held Held ADSR Reset Functions Functions...
Page 327 Figure 12-3 Typical A/D Converter Operation Timing...
Page 328 Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRRH/ADRRL data Perform A/D conversion? Figure 12-4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
Page 329: Application Notes
Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Perform A/D conversion? Figure 12-5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) 12.6 Application Notes •...
Page 330: Section 13 Lcd Controller/Driver
Section 13 LCD Controller/Driver 13.1 Overview The H8/3867 Series and H8/3827 Series has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 13.1.1 Features 1. Features Features of the LCD controller/driver are given below. •...
Page 331: Block Diagram
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the LCD controller/driver. LCD drive power supply (built-in step-up constant- voltage circuit) ø/2 to ø/256 Common Common ø data latch driver LPCR LCR2 Segment 32-bit shift Display timing generator driver register LCD RAM (32 bytes)
Page 332: Pin Configuration
13.1.3 Pin Configuration Table 13=1 shows the LCD controller/driver pin configuration. Table 13-1 Pin Configuration Name Abbrev. Function Segment output pins to SEG Output LCD segment drive pins All pins are multiplexed as port pins (setting programmable) Common output pins to COM Output LCD common drive pins...
Page 333 13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR) DTS1 DTS0 SGS3 SGS2 SGS1 SGS0 Initial value Read/Write LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions. LPCR is initialized to H'00 upon reset. Bits 7 to 5: Duty cycle select 1 and 0 (DTS1, DTS0), common function select (CMX) The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty.
Page 334 Bit 7 Bit 6 Bit 5 DTS1 DTS0 Duty Cycle Common Drivers Notes Static (initial value) Do not use COM , COM , and to COM , COM , and COM output the same waveform as COM 1/2 duty to COM Do not use COM and COM to COM...
Page 335 Bit 3: Segment driver select 3 to 0 (SGS3 to SGS0) Bits 3 to 0 select the segment drivers to be used. Function of Pins SEG to SEG Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SGS3 SGS2 SGS1 SGS0 SEG Notes Port Port...
Page 336: Lcd Control Register (Lcr)
13.2.2 LCD Control Register (LCR) — DISP CKS3 CKS2 CKS1 CKS0 Initial value Read/Write — LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset. Bit 7: Reserved bit Bit 7 is reserved;...
Page 337 Bit 4: Display data control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP Description Blank data is displayed (initial value) LCD RAM data is display Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency.
Page 338: Lcd Control Register 2 (Lcr2)
13.2.3 LCD Control Register 2 (LCR2) LCDAB — — SUPS CDS3 CDS2 CDS1 CDS0 Initial value Read/Write — — LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform, selects the drive power supply, controls the step-up constant-voltage (5 V) power supply, and selects the duty cycle of the charge/discharge pulses which control disconnection of the power supply split-resistance from the power supply circuit.
Page 339 Bits 3 to 0: Charge/discharge pulse duty cycle select (CDS3 to CDS0) Bit 3 Bit 2 Bit 1 Bit 0 CDS3 CDS2 CDS1 CDS0 Duty Cycle Notes Fixed high (initial value) Fixed low 1/16 1/32 *: Don’t care Bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power supply circuit.
Page 340: Clock Stop Register 2 (Ckstpr2)
13.2.4 Clock Stop Register 2 (CKSTPR2) — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the LCD controller/driver is described here. For details of the other bits, see the sections on the relevant modules.
Page 341: Operation
13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. Hardware settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V and V as shown in figure 13-3.
Page 342 chip power supply circuit, or by using an external circuit. With the H8/3867 Series, the on-chip power supply circuit allows the selection of either the power supply voltage (V or a step-up constant voltage (5 V). For details of the step-up constant-voltage power supply, see 13.3.4, Step-Up Constant-Voltage (5 V) Power Supply.
Page 343 2. Software settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS to SGS c.
Page 344 13.3.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles when segment external expansion is not used are shown in figures 13-5 to 13-8, and LCD RAM maps when segment external expansion is used in figures 13-9 to 13-12.
Page 345 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 H'F74F Space not used for display Figure 13-6 LCD RAM Map when Not Using Segment External Expansion (1/3 Duty)
Page 346 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 Display space H'F747 Space not used for display H'F74F Figure 13-7 LCD RAM Map when Not Using Segment External Expansion (1/2 Duty)
Page 347 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 Display space H'F743 Space not used for display H'F74F Figure 13-8 LCD RAM Map when Not Using Segment External Expansion (Static Mode)
Page 348 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 Expansion driver display space H'F75F Figure 13-9 LCD RAM Map when Using Segment External Expansion (SGX = “1”, SGS3 to SGS0 = “0000” 1/4 Duty)
Page 349 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 Expansion driver display space H'F75F Space not used for display Figure 13-10 LCD RAM Map when Using Segment External Expansion (SGX = “1”, SGS3 to SGS0 = “0000” 1/3 Duty)
Page 350 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 Expansion driver display space H'F75F Figure 13-11 LCD RAM Map when Using Segment External Expansion (SGX = “1”, SGS3 to SGS0 = “0000” 1/2 Duty)
Page 351 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 H'F740 Expansion driver display space H'F75F Figure 13-12 LCD RAM Map when Using Segment External Expansion (SGX = “1”, SGS3 to SGS0 = “0000” Static)
Page 352 13.3.3 Luminance Adjustment Function (V0 Pin) Figure 13-13 shows a detailed block diagram of the LCD drive power supply unit. The voltage output to the V pin is either V or the 5 V output from the step-up conversion power supply circuit.
Page 353: Step-Up Constant-Voltage (5 V) Power Supply
13.3.4 Step-Up Constant-Voltage (5 V) Power Supply The H8/3867 Series has an on-chip step-up constant-voltage (5 V) power supply which enables a 5 V constant voltage to be obtained independently of V . This feature is not provided in the H8/3827 Series.
Page 354 2. Example of operation (with 1/3 bias drive) 1. During charging period Tc in the figure, the potential is divided among pins V1, V2, and V3 by the built-in split-resistance (the potential of V2 being 2/3 that of V1, and that of V3 being 1/3 that of V1), as shown in figure 13-14, and external capacitors C1, C2, and C3 are charged.
Page 355 1 frame 1 frame Data Data (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame Data Data (d) Waveform with static output (c) Waveform with 1/2 duty Figure 13-15 Output Waveforms for Each Duty Cycle (A Waveform)
Page 356 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Data Data (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Data...
Page 357: Operation In Power-Down Modes
Table 13-3 Output Levels Data Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty Common output Segment output 13.3.6 Operation in Power-Down Modes In the H8/3867 Series, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 13-4.
Page 358: Boosting The Lcd Drive Power Supply
13.3.7 Boosting the LCD Drive Power Supply When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power supply capacity is insufficient when using the step-up constant power supply (5 V), either use V as the power supply or use an external power supply circuit.
Page 359: Connection To Hd66100
13.3.8 Connection to HD66100 If the segments are to be expanded externally, an HD66100 should be connected. Connecting one HD66100 provides 80-segment expansion. When carrying out external expansion, select the external expansion signal function of pins SEG to SEG with the SGX bit in LPCR, and set bits SGS3 to SGS0 to 0000 or 0001.
Page 360 H8/3867 Series chip HD66100 (a) 1/3 bias, 1/4 or 1/3 duty H8/3867 Series chip HD66100 (b) 1/2 duty H8/3867 Series chip HD66100 (c) Static mode Figure 13-18 Connection to HD66100...
Page 361: Section 14 Power Supply Circuit
Section 14 Power Supply Circuit 14.1 Overview The H8/3867 Series incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 1.5 V, independently of the voltage of the power supply connected to the external V pin.
Page 362: When Not Using The Internal Power Supply Step-Down Circuit
14.3 When Not Using the Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and CV pin, as shown in figure 14-2. The external power supply is then input directly to the internal power supply.
Page 363: Section 15 Electrical Characteristics
Section 15 Electrical Characteristics 15.1 H8/3867 Series and H8/3827 Series Absolute Maximum Ratings Table 15-1 lists the absolute maximum ratings. Table 15-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage , CV –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Programming voltage –0.3 to +13.0...
Page 364: H8/3867 Series And H8/3827 Series Electrical Characteristics
15.2 H8/3867 Series and H8/3827 Series Electrical Characteristics 15.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 38.4 32.768 •...
Page 365 Power supply voltage and operating frequency range 19.2 16.384 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) • Internal power supply step-down circuit not used 4.096 • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 62.5 4.096 •...
Page 366 3. Analog power supply voltage and A/D converter operating range • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode • Internal power supply step-down circuit • Internal power supply step-down circuit not used not used •...
Page 367 15.2.2 DC Characteristics Table 15-2 lists the DC characteristics of the H8/3864. Table 15-2 DC Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated.
Page 368: Dc Characteristics
Table 15-2 DC Characteristics (cont) = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Unit Test Condition Notes...
Page 369 Table 15-2 DC Characteristics (cont) = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Unit Test Condition Notes...
Page 370 Table 15-2 DC Characteristics (cont) = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Unit Test Condition Notes...
Page 371 RAM data — — retaining voltage Notes: 1. Applies to the Mask ROM products. 2. Applies to the HD6473867 and HD6473827. 3. Pin states during current measurement. Other LCD Power RES Pin Mode Internal State Pins Supply...
Page 372 Table 15-2 DC Characteristics (cont) = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Unit Test Condition Notes...
Page 373: Ac Characteristics
15.2.3 AC Characteristics Table 15-3 lists the control signal timing, and tables 15-4 lists the serial interface timing of the H8/3864. Table 15-3 Control Signal Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C...
Page 374 Table 15-3 Control Signal Timing (cont) = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Applicable Reference Item Symbol Pins Min Typ...
Page 375 Table 15-4 Serial Interface (SCI3-1, SCI3-2) Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Reference Item Symbol Unit Test Conditions...
Page 376: A/D Converter Characteristics
15.2.4 A/D Converter Characteristics Table 15-5 shows the A/D converter characteristics of the H8/3864. Table 15-5 A/D Converter Characteristics = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise indicated. Values Applicable Reference...
Page 377: Lcd Characteristics
15.2.5 LCD Characteristics Table 15-6 shows the LCD characteristics. Table 15-6 LCD Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (including subactive mode) unless otherwise specified. Values Applicable Test Reference...
Page 378: Operation Timing
15.3 Operation Timing Figures 15-1 to 15-6 show timing diagrams. , tw OSC1 Figure 15-1 Clock Input Timing Figure 15-2 RES Low Width to IRQ to WKP ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH Figure 15-3 Input Timing...
Page 379 Figure 15-4 UD Pin Minimum Modulation Width Timing SCKW scyc Figure 15-5 SCK3 Input Clock Timing...
Page 380 scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 1/2Vcc + 0.2 V Output low = 0.8 V Load conditions are shown in figure 15-8. Figure 15-6 SCI3 Synchronous Mode Input/Output Timing...
Page 381 – 0.5V 0.4V – 0.5V 0.4V – 0.5V 0.4V 0.4V Figure 15-7 Segment Expansion Signal Timing...
Page 382: Output Load Circuit
15.4 Output Load Circuit 2.4 kΩ Output pin 12 k Ω 30 pF Figure 15-8 Output Load Condition 15.5 Resonator Equivalent Circuit Crystal Resonator Parameter Ceramic Resonator Parameters Frequency Frequency 4.193 (MHz) (MHz) 40 Ω 100 Ω 8.6 Ω 8.8 Ω (max) (max) (max)
Page 383: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 384 Table A-1 lists the H8/300L CPU instruction set. Table A-1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — 2 B Rs8 → Rd8 MOV.B Rs, Rd —...
Page 385 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — B Rd8+Rs8 → Rd8 ADD.B Rs, Rd — W Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
Page 386 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8 × Rs8 → Rd16 MULXU.B Rs, Rd — — — — — — 14 B Rd16÷Rs8 → Rd16 DIVXU.B Rs, Rd —...
Page 387 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C ROTL.B Rd — — ROTR.B Rd — — B (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — 2 B (#xx:3 of @Rd16) ←...
Page 388 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B (#xx:3 of Rd8) → Z BTST #xx:3, Rd — — — — — 2 B (#xx:3 of @Rd16) → Z BTST #xx:3, @Rd —...
Page 389 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Branching Condition Mnemonic Operation I H N Z V C B C∨(#xx:3 of @aa:8) → C BIOR #xx:3, @aa:8 — — — — — B C⊕(#xx:3 of Rd8) → C BXOR #xx:3, Rd —...
Page 390 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C — SP–2 → SP JSR @Rn — — — — — — 6 PC → @SP PC ← Rn16 — SP–2 → SP JSR @aa:16 —...
Page 391: Operation Code Map
A.2 Operation Code Map Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 392 Table A-2 Operation Code Map High SLEEP XORC ANDC ADDS ADDX SHLL SHLR ROTXL ROTXR SUBS SUBX SHAL SHAR ROTL ROTR MULXU DIVXU BIST BSET BNOT BCLR BTST BXOR BAND EEPMOV Bit-manipulation instructions BIOR BIXOR BIAND BILD ADDX SUBX Note: The PUSH and POP instructions are identical in machine language to MOV instructions.
Page 393: Number Of Execution States
A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I ×...
Page 394 Table A-3 Number of Cycles in Each Instruction Access Location Execution Status (instruction cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access — Internal operation Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details.
Page 395 Table A-4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 396 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd...
Page 397 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd...
Page 398 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B @(d:16, Rs), Rd 2 MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) 2 MOV.B Rs, @–Rd...
Page 399 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd...
Page 400: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers B.1 Addresses Bit Names Lower Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'90 WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System control H'91 SPCR...
Page 401 Bit Names Lower Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'B1 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Timer A H'B2 TCSRW B6WI TCWE B4WI TCSRWE B2WI WDON BOW1...
Page 402 Bit Names Lower Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'D5 I/O Port H'D6 PDR3 H'D7 PDR4 — — — — H'D8 PDR5 H'D9 PDR6 H'DA PDR7 H'DB PDR8...
Page 403 Bit Names Lower Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'F9 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 System control H'FA CKSTPR1 — S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP...
Page 404: Functions
B.2 Functions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module TMC—Timer mode register C H'B4 Timer C numbers Initial bit TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 values Names of the Initial value bits.
Page 405: System Control
WEGR—Wakeup Edge Select Register H'90 System control WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WKPn edge selected WKPn pin falling edge detected WKPn pin rising edge detected (n = 0 to 7) SPCR—Serial Port Control Register H'91 —...
Page 406 CWOSR—Subclock Output Select Register H'92 Timer A — — — — — — — CWOS Initial value Read/Write TMOW pin clock select Clock output from TMA is output ø is output...
Page 407 ECCSR—Event counter control/status register H'95 — CUEH CUEL CRCH CRCL Initial value Read/Write Counter reset control L ECL is reset ECL reset is cleared and count-up function is enabled Counter reset control H ECH is reset ECH reset is cleared and count-up function is enabled Count-up enable L ECL event clock input is disabled.
Page 408 ECH—Event counter H H'96 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial value Read/Write ECL—Event counter L H'97 ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial value Read/Write...
Page 409 SMR31—Serial mode register 31 H'98 SCI31 COM31 CHR31 PE31 PM31 STOP31 MP31 CKS311 CKS310 Initial value Read/Write Clock select ø clock øw/2 clock ø/16 clock ø/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit 2 stop bits Parity mode...
Page 410 BRR31—Bit rate register31 H'99 SCI31 BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310 Initial value Read/Write...
Page 411 SCR31—Serial control register 31 H'9A SCI31 TIE31 RIE31 TE31 RE31 MPIE31 TEIE31 CKE311 CKE310 Initial value Read/Write Clock enable Description Bit 0 Bit 1 CKE311 CKE310 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock...
Page 412 TDR31—Transmit data register 31 H'9B SCI31 TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 Initial value Read/Write Data for transfer to TSR...
Page 413 SSR31—Serial status register31 H'9C SCI3 TDRE31 RDRF31 OER31 FER31 PER31 TEND31 MPBR31 MPBT31 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmit end Transmission in progress...
Page 414 RDR31—Receive data register 31 H'F9D SCI31 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 Initial value Read/Write...
Page 415 SMR32—Serial mode register 32 H'A8 SCI32 COM32 CHR32 PE32 PM32 STOP32 MP32 CKS321 CKS320 Initial value Read/Write Clock select ø clock øw/2 clock ø/16 clock ø/64 clock Multiprocessor mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop bit length 1 stop bit 2 stop bits Parity mode...
Page 416 BRR32—Bit rate register 32 H'A9 SCI32 BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120 Initial value Read/Write...
Page 417 SCR32—Serial control register 32 H'AA SCI32 TIE32 RIE32 TE32 RE32 MPIE32 TEIE32 CKE321 CKE320 Initial value Read/Write Clock enable Description Bit 1 Bit 0 CKE321 CKE320 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock...
Page 418 TDR32—Transmit data register 32 H'AB SCI32 TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320 Initial value Read/Write Data for transfer to TSR...
Page 419 SSR32—Serial status register 32 H'AC SCI32 TDRE32 RDRF32 OER32 FER32 PER32 TEND32 MPBR32 MPBT32 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmit end...
Page 420 RDR32—Receive data register 32 H'AD SCI32 RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320 Initial value Read/Write TMA—Timer mode register A H'B0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select Internal clock select ø/32 Prescaler and Divider Ratio TMA3 TMA2...
Page 421 TCA—Timer counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value...
Page 422 TCSRW—Timer control/status register W H'B2 Watchdog timer B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write R/(W) R/(W) R/(W) R/(W) Watchdog timer reset 0 [Clearing conditions] • Reset by RES pin • When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit...
Page 423 TCW—Timer counter W H'B3 Watchdog timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TMC—Timer mode register C H'B4 Timer C TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 Initial value Read/Write — — Clock select Internal clock: ø/8192 Internal clock:...
Page 424 TCC—Timer counter C H'B5 Timer C TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write Count value TLC—Timer load register C H'B5 Timer C TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value Read/Write Reload value...
Page 425 TCRF—Timer control register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Clock select L Counting on external event (TMIF) rising/falling edge Internal clock ø/32 Internal clock ø/16 Internal clock ø/4 Internal clock øw/4 Toggle output level L Low level High level...
Page 426 TCSRF—Timer control/status register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Counter clear L TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled Timer overflow interrupt enable L TCFL overflow interrupt request is disabled TCFL overflow interrupt request is enabled...
Page 427 TCFH—8-bit timer counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value Read/Write Count value TCFL—8-bit timer counter FL H'B9 Timer F TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0 Initial value Read/Write Count value OCRFH—Output compare register FH H'BA Timer F...
Page 428 TMG—Timer mode register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value Read/Write R/(W)* R/(W)* Clock select Internal clock: counting on ø/64 Internal clock: counting on ø/32 Internal clock: counting on ø/2 Internal clock: counting on øw/4 Counter clear TCG clearing is disabled TCG cleared by falling edge of input capture input signal...
Page 429 ICRGF—Input capture register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write ICRGR—Input capture register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value Read/Write LPCR—LCD port control register H'C0 LCD controller/driver DTS1...
Page 430 LCR—LCD control register H'C1 LCD controller/driver — DISP CKS3 CKS2 CKS0 CKS1 Initial value Read/Write — Frame frequency select Bit 1 Bit 1 Bit 3 Bit 2 Operating Clock CKS2 CKS3 CKS1 CKS0 øw øw øw/2 ø/2 ø/4 ø/8 ø/16 ø/32 ø/64 ø/128...
Page 431 LCR2—LCD control register 2 H'C2 LCDAB — — SUPS CDS3 CDS2 CDS1 CDS0 Initial value Read/Write — — Charge/discharge pulse duty cycle select Bit 2 Bit 1 Bit 1 Bit 3 Duty Cycle CDS2 CDS3 CDS1 CDS0 1/16 1/32 : Don’t care 5 V regulator control 5 V regulator halted 5 V regulator operates...
Page 432 AMR—A/D mode register H'C6 A/D converter TRGE — — Initial value Read/Write — — Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected * : Don’t care External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select...
Page 433 ADRRH—A/D result register H H'C4 A/D converter ADRRL—A/D result register L H'C5 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Initial value Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Read/Write R/(W) R/(W) R/(W)
Page 434 PMR1—Port mode register 1 H'C8 I/O port IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) /TMOW pin function switch Functions as P1 I/O pin 1 Functions as TMOW output pin /TMOFL pin function switch 0 Functions as P1 I/O pin...
Page 435 PMR3—Port mode register 3 H'CA I/O port AEVL AEVH WDCKS IRQ0 RESO Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) /PWM pin function switch 0 Functions as P3 I/O pin 1 Functions as PWM output pin /UD pin function switch 0 Functions as P3 I/O pin 1 Functions as UD input pin...
Page 436 PMR5—Port mode register 5 H'CC I/O port PWCR—PWM control register H'D0 14-bit PWM — — — — — — PWCR1 PWCR0 Initial value Read/Write — — — — — — Clock select 0 The input clock is ø/2 (tø* = 2/ø) The conversion period is 16,384/ø, with a minimum modulation width of 1/ø...
Page 437 PWDRU—PWM data register U H'D1 14-bit PWM — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0 Initial value Read/Write — — Upper 6 bits of data for generating PWM waveform PWDRL—PWM data register L H'D2 14-bit PWM PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0...
Page 438 PDR4—Port data register 4 H'D7 I/O ports — — — — Initial value Read/Write — — — — PDR5—Port data register 5 H'D8 I/O ports Initial value Read/Write PDR6—Port data register 6 H'D9 I/O ports Initial value Read/Write PDR7—Port data register 7 H'DA I/O ports Initial value...
Page 439 PDRA—Port data register A H'DD I/O ports — — — — Initial value Read/Write — — — — PDRB—Port data register B H'DE I/O ports Initial value Read/Write PUCR1—Port pull-up control register 1 H'E0 I/O ports PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1...
Page 440 PUCR6—Port pull-up control register 6 H'E3 I/O ports PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 Initial value Read/Write PCR1—Port control register 1 H'E4 I/O ports PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 Initial value Read/Write Port 1 input/output select 0 Input pin 1 Output pin PCR3—Port control register 3...
Page 441 PCR5—Port control register 5 H'E8 I/O ports PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 Initial value Read/Write Port 5 input/output select 0 Input pin 1 Output pin PCR6—Port control register 6 H'E9 I/O ports PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6...
Page 442 PCR8—Port control register 8 H'EB I/O ports PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 Initial value Read/Write Port 8 input/output select 0 Input pin 1 Output pin PCRA—Port control register A H'ED I/O ports — — — — PCRA PCRA PCRA PCRA...
Page 443 SYSCR1—System control register 1 H'F0 System control SSBY STS2 STS1 STS0 LSON — Initial value Read/Write — Active (medium-speed) mode clock select ø ø ø ø /128 Low speed on flag 0 The CPU operates on the system clock (ø) 1 The CPU operates on the subclock (ø...
Page 444 SYSCR2—System control register 2 H'F1 System control — — — NESEL DTON MSON Initial value Read/Write — — — Subactive mode clock select ø /8 ø /4 ø /2 Medium speed on flag *: Don’t care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag 0 •...
Page 445 IEGR—IRQ edge select register H'F2 System control — — — IEG4 IEG3 IEG2 IEG1 IEG0 Initial value Read/Write — — — edge select 0 Falling edge of IRQ pin input is detected Rising edge of IRQ pin input is detected edge select 0 Falling edge of IRQ , TMIC pin input is detected...
Page 446 IENR1—Interrupt enable register 1 H'F3 System control IENTA — IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value Read/Write to IRQ interrupt enable 0 Disables IRQ to IRQ interrupt requests Enables IRQ to IRQ interrupt requests Wakeup interrupt enable 0 Disables WKP to WKP interrupt requests Enables WKP...
Page 447 IENR2—Interrupt enable register 2 H'F4 System control IENDT IENAD — IENTG IENTFH IENTFL IENTC IENEC Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) Asynchronous event counter interrupt enable 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests Timer C interrupt enable 0 Disables timer C interrupt requests...
Page 448 IRR1—Interrupt request register 1 H'F6 System control IRRTA — — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value Read/Write R/W* R/W* — R/W* R/W* R/W* R/W* IRQ4 to IRQ0 interrupt request flags 0 Clearing conditions: When IRRIn = 1, it is cleared by writing 0 1 Setting conditions: When pin IRQn is designated for interrupt input and the designated signal edge is input...
Page 449 IRR2—Interrupt request register 2 H'F7 System control IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTC IRREC Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Asynchronous event counter interrupt request flag 0 Clearing conditions: When IRREC = 1, it is cleared by writing 0 1 Setting conditions: When the asynchronous event counter value overflows Timer C interrupt request flag...
Page 450 IWPR—Wakeup interrupt request register H'F9 System control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Wakeup interrupt request register 0 Clearing conditions: When IWPFn = 1, it is cleared by writing 0 1 Setting conditions: When pin WKPn is designated for wakeup input and a falling edge is input at that pin...
Page 451 CKSTPR1—Clock stop register 1 H'FA System control — S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value Read/Write Timer A module standby mode control 0 Timer A is set to module standby mode Timer A module standby mode is cleared Timer C module standby mode control Timer C is set to module standby mode Timer C module standby mode is cleared...
Page 452 CKSTPR2—Clock stop register 2 H'FB System control — — — — AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value Read/Write — — — — LCD module standby mode control 0 LCD is set to module standby mode LCD module standby mode is cleared PWM module standby mode control 0 PWM is set to module standby mode PWM module standby mode is cleared...
Page 453: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 n–4 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 7 to 4...
Page 454 PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG Figure C-1 (b) Port 1 Block Diagram (Pin P1...
Page 455 Timer F module TMOFH (P1 TMOFL (P1 PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n= 2, 1 Figure C-1 (c) Port 1 Block Diagram (Pin P1 , P1...
Page 456 Timer A module TMOW PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C-1 (d) Port 1 Block Diagram (Pin P1...
Page 457: Block Diagrams Of Port 3
C.2 Block Diagrams of Port 3 PUCR3 PMR3 PDR3 PCR3 AEC module AEVH(P3 AEVL(P3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n=7 to 6 Figure C-2 (a) Port 3 Block Diagram (Pin P3 to P3...
Page 458 PUCR3 SCINV1 SPC31 SCI31 module TXD31 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 Figure C.2 (b) Port 3 Block Diagram (Pin P3...
Page 459 PUCR3 SCI31 module RE31 RXD31 PDR3 PCR3 SCINV0 PDR3: Port data register 3 PCR3: Port control register 3 Figure C.2 (c) Port 3 Block Diagram (Pin P3...
Page 460 PUCR3 SCI31 module SCKIE31 SCKOE31 SCKO31 SCKI31 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 Figure C.2 (d) Port 3 Block Diagram (Pin P3...
Page 461 RESO PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.2 (e) Port 3 Block Diagram (Pin P3...
Page 462 PUCR3 PMR3 PDR3 PCR3 Timer C module PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C-2 (f) Port 3 Block Diagram (Pin P3...
Page 463 PWM module PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C-2 (g) Port 3 Block Diagram (Pin P3...
Page 464: Block Diagrams Of Port 4
C.3 Block Diagrams of Port 4 PMR4 PMR4: Port mode register 4 Figure C.3 (a) Port 4 Block Diagram (Pin P4...
Page 465 SCINV3 SPC32 SCI32 module TXD32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3 (b) Port 4 Block Diagram (Pin P4...
Page 466 SCI32 module RE32 RXD32 PDR4 PCR4 SCINV2 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3 (c) Port 4 Block Diagram (Pin P4...
Page 467 SCI32 module SCKIE32 SCKOE32 SCKO32 SCKI32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3 (d) Port 4 Block Diagram (Pin P4...
Page 468: Block Diagram Of Port 5
C.4 Block Diagram of Port 5 PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.4 Port 5 Block Diagram...
Page 469: Block Diagram Of Port 6
C.5 Block Diagram of Port 6 PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.5 Port 6 Block Diagram...
Page 470: Block Diagram Of Port 7
C.6 Block Diagram of Port 7 PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.6 Port 7 Block Diagram...
Page 471: Block Diagrams Of Port 8
C.7 Block Diagrams of Port 8 PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n= 7 to 0 Figure C-7 Port 8 Block Diagram...
Page 472: Block Diagram Of Port A
C.8 Block Diagram of Port A PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.8 Port A Block Diagram...
Page 473: Block Diagram Of Port B
C.9 Block Diagram of Port B Internal data bus A/D module AMR3 to AMR0 n = 7 to 0 Figure C-9 Port B Block Diagram...
Page 474: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Table D-1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active High Retained Retained High Retained Functions Functions impedance impedance* to P3 High Retained Retained High Retained Functions Functions impedance* impedance* to P4...
Page 475: Appendix E List Of Product Codes
Appendix E List of Product Codes Table E.1 H8/3864 Series Product Code Lineup Package Product Type Product Code Mark Code (Hitachi Package Code) H8/3867 H8/3862 Mask ROM HD6433862H HD6433862(***)H 80-pin QFP (FP-80A) Series versions HD6433862F HD6433862(***)F 80-pin QFP (FP-80B) HD6433862W...
Page 476 Table E.1 H8/3864 Series Product Code Lineup (cont) Package Product Type Product Code Mark Code (Hitachi Package Code) H8/3827 H8/3825 Mask ROM HD6433825H HD6433825(***)H 80-pin QFP (FP-80A) Series versions HD6433825F HD6433825(***)F 80-pin QFP (FP-80B) HD6433825W HD6433825(***)W 80-pin TQFP (TFP-80C) H8/3826...
Page 477: Appendix F Package Dimensions
17.2 ± 0.3 Unit: mm *0.32 ± 0.08 0.12 M 0.30 ± 0.06 0.83 0° – 8° 0.8 ± 0.3 0.10 Hitachi Code FP-80A JEDEC — EIAJ Conforms *Dimension including the plating thickness Weight (reference value) 1.2 g Base material dimension...
Page 478 24.8 ± 0.4 Unit: mm *0.37 ± 0.08 0.15 M 0.35 ± 0.06 0° – 10° 1.2 ± 0.2 0.15 Hitachi Code FP-80B JEDEC — EIAJ — *Dimension including the plating thickness Weight (reference value) 1.7 g Base material dimension...
Page 479 14.0 ± 0.2 Unit: mm *0.22 ± 0.05 0.10 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code TFP-80C JEDEC — EIAJ Conforms *Dimension including the plating thickness Base material dimension Weight (reference value) 0.4 g...
Page 480 Publication Date: 1st Edition, November 1997 3rd Edition, February 1999 Published by: ELectronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.

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Hitachi HD6473867 Hardware Manual

Section 1 Overview

Cpu

Exception Handling

Clock Pulse Generators

Power-Down Modes

Rom

Ram

I/O Ports

Timers

Section 10 Serial Communication Interface

Section 11 14-Bit PWM

Section 12 A/D Converter

Section 13 LCD Controller/Driver

Section 14 Power Supply Circuit

Section 15 Electrical Characteristics

Appendix A CPU Instruction Set

Appendix B Internal I/O Registers

Appendix C I/O Port Block Diagrams

Appendix D Port States in the Different Processing States

Appendix E List of Product Codes

Appendix F Package Dimensions

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Summary of Contents for Hitachi HD6473867