Parity Control Register (Pcr) Bsc - Hitachi SH7032 Hardware Manual

A.2.45 Parity Control Register (PCR)
• Start Address: H'5FFFFAA
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.46 PCR Bit Functions
Bit Bit Name
15 Parity error flag (PEF)
14 Parity forced output
(PFRC)
13 Parity polarity (PEO)
12,11 Parity check enable 1, 0
(PCHK1, PCHK0)
15 14 13
PEF PFRC PEO
0 0
R/W R/W R/W
7 6
— — —
0 0
— — —
Value
0
1
0
1
0
1
0 0
0 1
1 0
1 1
12 11
PCHK1 PCHK0
0 0 0
R/W R/W
5 4 3
— —
0 0 0
— —
Description
No parity error
Clear Condition: PEF read, then 0 written in PEF
Parity error occurred
No forced parity output
Forced high-level output
Even parity
Odd parity
Parity not checked or generated
Parity checked and generated in DRAM space
Parity checked and generated in DRAM space and
area 2
Reserved
BSC
10 9 8
— — —
0 0 0
— — —
2 1 0
— — —
0 0 0
— — —
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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