Register Descriptions; Dma Source Address Registers 0-3 (Sar0-Sar3); Dma Destination Address Registers 0-3 (Dar0-Dar3) - Hitachi SH7032 Hardware Manual

9.2

Register Descriptions

9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the
source address of a DMA transfer. During a DMA transfer, these registers indicate the next source
address (in single-address mode, SAR is ignored in transfers from external devices with DACK to
memory-mapped external devices or external memory).
The initial value after a reset or in standby mode is undefined.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address (in single-address mode, DAR is ignored in transfers from memory-
mapped external devices or external memory to external devices with DACK). The initial value
after a reset or in standby mode is undefined.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
180
31 30 29
— — —
R/W R/W R/W
23 22 21
— — —
R/W R/W R/W
31 30 29
— — —
R/W R/W R/W
23 22 21
— — —
R/W R/W R/W
28 27 26
— — —
R/W R/W R/W
...
...
...
...
28 27 26
— — —
R/W R/W R/W
...
...
...
...
25 24
— —
R/W R/W
0
—
R/W
25 24
— —
R/W R/W
0
—
R/W