Instruction Fetch Break - Hitachi SH7032 Hardware Manual

6.5.3

Instruction Fetch Break

If a break is attempted at the task A return destination instruction fetch, task B is activated before
the UBC interrupt by interrupt B generated during task A processing, and the UBC interrupt is
handled after the interrupt B exception handling.
(1) Cause
The SH7032/SH7034 chip operates as follows.
<Address>
0x00011a0a
Break
0x00011a0c
condition
0xf000974
(0xf000978 Overrun fetch)
0x02000030
It actually takes at least two cycles for the UBC interrupt generated by the address 0x00011a0c
instruction fetch cycle to be sent to the interrupt controller and interrupt exception handling to
begin. However, as shown in figure 6.3, when the UBC interrupt is generated, previously
generated interrupt B initiated by task B is accepted first, and the UBC interrupt is accepted after
completion of the interrupt B exception handling.
(2) Remedy
There is no way of preventing this operation by hardware. A software solution, such as the use of
a flag, must be employed.
Interrupt B accepted
Interrupt exception
F D E E
F
<Description>
Instruction replaced by interrupt
exception handling
Overrun fetch
Task B first instruction fetch
(instruction replaced by interrupt
exception handling)
UBC first instruction fetch
Figure 6.3 UBC Operation
UBC interrupt accepted
handling
M M E M E E
F D E E
f
Interrupt exception
handling
M M E M E E
F
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