Hitachi SH7032 Hardware Manual page 246

CK
DREQ
Bus
CPU CPU CPU DMAC DMAC DMAC CPU
cycle
DACK
Figure 9.23 DREQ Pin Sampling Timing in Burst Mode (Single Address DREQ Level
Detection, DACK Active-Low, 1 Bus Cycle = 2 States)
CK
DREQ
Bus
CPU CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) CPU
cycle
DACK
Figure 9.24 DREQ Pin Sampling Timing in Burst Mode (Dual Address DREQ Level
Detection, DACK Active-Low, DACK Output in Read Cycle, 1 Bus Cycle = 2 States)
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