Refresh Control - Hitachi SH7032 Hardware Manual

• RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a
DRAM access pauses for access to another space. Burst operation continues only while
DRAM access is continuous. Figure 8.28 shows the timing when an external memory space
access occurs during burst operation in RAS up mode.
T
p
CK
A21–
A0
Row address
RAS
CAS
AD15–
AD0
8.5.6

Refresh Control

The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit
(RMODE) in the refresh control register (RCR), either CAS-before-RAS refresh (CBR) or self-
refresh can be selected. When no refresh is performed, the refresh timer counter (RTCNT) can be
used as an 8-bit interval timer.
CAS-Before-RAS Refresh (CBR): A refresh is performed at an interval determined by the input
clock selected with clock select bits 2–0 (CKS2–CKS0) in the refresh timer control/status register
(RTCSR) and the value set in the refresh time constant register (RTCOR). Set the values of
RTCOR and CKS2–CKS0 so they satisfy the refresh interval specifications of the DRAM being
used.
To perform a CBR refresh, clear the RMODE bit in RCR to 0 and then set the refresh control bit
(RFSHE) bit to 1. Also write the required values to RTCNT and RTCOR. When the clock is
subsequently selected with the CKS2–CKS0 bits in RTCSR, RTCNT will begin to increment from
its current value. The RTCNT value is constantly compared with the RTCOR value and a CBR
refresh is performed when they match. RTCNT is simultaneously cleared to H'00 and
incrementing begins again.
DRAM access
T T T
r c
Column Column
address 1 address 2
Data 1
Figure 8.28 RAS Up Mode
External memory
space access
DRAM access
T1 T
c p
External memory
address
Row address
Data 2
External
memory data
T T
r c
Column
address 3
Data 3
155