Hitachi SH7032 Hardware Manual page 283

Table 10.10 Timer Interrupt Enable Register (TIER)
Channel
0
1
2
3
4
Bit:
Bit name:
Initial value:
R/W:
Note: * Undefined
• Bits 7–3 (Reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
• Bit 2 (Overflow Interrupt Enable (OVIE)): When the TSR overflow flag (OVF) is set to 1,
OVIE enables or disables interrupt requests from OVF.
Bit 2: OVIE
0
1
• Bit 1 (Input Capture/Compare Match Interrupt Enable B (IMIEB)): When the IMFB bit in TSR
is set to 1, IMIEB enables or disables interrupt requests by IMFB.
Bit 1: IMIEB
0
1
• Bit 0 (Input Capture/Compare Match Interrupt Enable A (IMIEA)): When the IMFA bit in
TSR is set to 1, IMIEA enables or disables interrupt requests by IMFA.
Bit 0: IMIEA
0
1
248
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
7 6
— —
1
*
— —
Description
Disables interrupt requests by OVF
Enables interrupt requests from OVF
Description
Disables interrupt requests by IMFB (IMIB)
Enables interrupt requests by IMFB (IMIB)
Description
Disables interrupt requests by IMFA (IMIA)
Enables interrupt requests by IMFA (IMIA)
Function
TIER controls interrupt enabling/disabling
5 4
— — —
1 1
— — —
3 2 1
OVIE IMIEB
1 0 0
R/W R/W
0
IMIEA
0
R/W
(Initial value)
(Initial value)
(Initial value)