Hitachi SH7032 Hardware Manual page 199

Table 8.12 Bus Cycle States when Accessing Address Spaces
Address Space
External memory (areas 1, 3–5, 7) 1 state fixed; WAIT signal
External memory (Areas 0, 2, 6;
long wait avail-able)
DRAM space (area 1)
Multiplexed I/O space (area 6)
On-chip supporting module space
(area 5)
On-chip ROM (area 0)
On-chip RAM (area 7)
Address Space
External memory (area 1)
External memory (areas 3–5, 7)
External memory (Areas
0, 2, 6; long wait available)
DRAM space (area 1)
Multiplexed I/O space (area 6)
On-chip peripheral module space
(area 5)
On-chip ROM (area 0)
On-chip RAM (area 7)
Note: * The number of long wait states (1 to 4) is set in WCR3.
For details on bus cycles when external spaces are accessed, see section 8.4, Accessing External
Memory Space, section 8.5, DRAM Interface Operation, and section 8.6, Address/Data
Multiplexed I/O Space Access.
164
CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC
Single Mode Memory Read/Write Cycle
Corresponding Bits in
WCR1 and WCR2 = 0
ignored
1 state + long wait state * ,
WAIT signal ignored
Column address cycle:
1 state, WAIT signal ignored
(short pitch)
4 states + wait states from WAIT signal
3 states fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
CPU Write Cycle, DMAC Dual Mode Memory Write Cycle
WW1 of WCR1=0
Setting prohibited
2 states + wait states from WAIT signal
1 state + long wait state * + wait states from WAIT signal
Column address cycle:
1 state, WAIT signal
ignored (short pitch)
4 states + wait states from WAIT signal
3 states fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
Corresponding Bits in
WCR1 and WCR2 = 1
2 states + wait states from
WAIT signal
1 state + long wait state * + wait
states from WAIT signal
Column address cycle:
2 states + wait states from
WAIT signal (long pitch)
(WW1 of WCR1)
WW1 of WCR1=1
2 states + wait state from
WAIT signal
Column address cycle:
2 states + wait states from
WAIT signal (long pitch)