Hitachi SH7032 Hardware Manual page 664

Table A.61 PACR2 Bit Functions
Bit Bit Name
14 PA7 mode bit (PA7MD)
12 PA6 mode bit (PA6MD)
10 PA5 mode bit (PA5MD)
8 PA4 mode bit (PA4MD)
7,6 PA3 mode bits 1,0
(PA3MD1, PA3MD0)
5,4 PA2 mode bits 1,0
(PA2MD1, PA2MD0)
3,2 PA1 mode bits 1,0
(PA1MD1, PA1MD0)
1,0 PA0 mode bits 1,0
(PA0MD1, PA0MD0)
Value Description
0 General-purpose input/output (PA7)
1 Bus request acknowledge output (BACK)
0 General-purpose input/output (PA6)
1 Read output (RD)
0 General-purpose input/output (PA5)
1 High write output (WRH) or low byte strobe output (LBS)
0 General-purpose input/output (PA4)
1 Low write output (WRL) or write output (WR)(Initial value)
0 0 General-purpose input/output (PA3)
0 1 Chip select output (CS7)
1 0 Wait state input (WAIT)
1 1 Reserved
0 0 General-purpose input/output (PA2)
0 1 Chip select output (CS6)
1 0 ITU input capture input/output compare output (TIOCB0)
1 1 Reserved
0 0 General-purpose input/output (PA1)
0 1 Chip select output (CS5)
1 0 Row address strobe output (RAS)
1 1 Reserved
0 0 General-purpose input/output (PA0)
0 1 Chip select output (CS4)
1 0 ITU input capture input/output compare output (TIOCA0)
1 1 Reserved
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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