Block Diagram - Hitachi SH7032 Hardware Manual

10.1.2

Block Diagram

ITU Block Diagram (Overall Diagram): Figure 10.1 shows a block diagram of the ITU.
TCLKA–TCLKD
φ, φ/2, φ/4, φ/8
TOCXA4, TOCXB4
TIOCA0–TIOCA4
TIOCB0–TIOCB4
TOCR: Timer output control register (8 bits)
TSTR: Timer start register (8 bits)
TSNC: Timer synchronization register (8 bits)
TMDR: Timer mode register (8 bits)
TFCR: Timer function control register (8 bits)
222
Clock Control
selection
Counter control and
pulse I/O control unit
Module data bus
Figure 10.1 Block Diagram of ITU
IMIA0–IMIA4
IMIB0–IMIB4
logic
OVI0–OVI4
TOCR
TSTR
TSNC
TMDR
TFCR
Internal
data
bus