Hitachi SH7032 Hardware Manual page 573

CK
A21–A0
RAS
CAS
RD (Write)
WRH, WRL ,
WR (Write)
AD15–AD0
DPH, DPL
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Figure 20.56 (b) DRAM Bus Cycle (Short-Pitch, High-Speed Page Mode: Write)
Note: For details of the silent cycle, see section 8.5.5, DRAM Burst Mode.
538
T T T
p r
t t
AD AD
Row address Column address
t
RASD1
t
WSD3
t
WDD2
t
WPDD2
t
DACD4
Silent
cycle
T
c c
Column address
t
ASC
t
WSD4
t
WDH
t
WPDH
t
DACD5
t
RASD2
t
DACD5